Clock tree distribution

The semiconductor industry is moving toward submicron and deep submicron (0.5 μm and below) technologies. As the chip size keeps decreasing, the chip capacity keeps increasing. New challenges are appearing on high speed ASIC (Application Specified Integrated Circuit) design. Building a balanced clock tree is now essential for the success of any advanced VLSI (Very Large Scale Integration) design. The interconnect wire delay is as important as the logic gate delay.

[1]  Mark Horowitz,et al.  Signal Delay in RC Tree Networks , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Chung-Kuan Cheng,et al.  On general zero-skew clock net construction , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[3]  Chung-Kuan Cheng,et al.  PAS: A stand alone placement annotation system for high speed designs , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

[4]  Majid Sarrafzadeh,et al.  A buffer distribution algorithm for high-performance clock net optimization , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[5]  Lawrence T. Pillage,et al.  Skew reduction in clock trees using wire width optimization , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.