A 512kb 8T SRAM macro operating down to 0.57V with an AC-coupled sense amplifier and embedded data-retention-voltage sensor in 45nm SOI CMOS
暂无分享,去创建一个
[1] Igor Arsovski,et al. Self-referenced sense amplifier for across-chip-variation immune sensing in high-performance Content-Addressable Memories , 2006, IEEE Custom Integrated Circuits Conference 2006.
[2] Leland Chang,et al. A 5.3GHz 8T-SRAM with Operation Down to 0.41V in 65nm CMOS , 2007, 2007 IEEE Symposium on VLSI Circuits.
[3] Wilfried Haensch,et al. Optimizing CMOS technology for maximum performance , 2006, IBM J. Res. Dev..
[4] Atila Alvandpour,et al. High–performance, low–power, and leakage–tolerance challenges for sub–70nm microprocessor circuits , 2002 .
[5] Naveen Verma,et al. A High-Density 45 nm SRAM Using Small-Signal Non-Strobed Regenerative Sensing , 2008, IEEE Journal of Solid-State Circuits.
[6] Jiajing Wang,et al. Canary Replica Feedback for Near-DRV Standby VDD Scaling in a 90nm SRAM , 2007, 2007 IEEE Custom Integrated Circuits Conference.
[7] V. De,et al. The scaling of data sensing schemes for high speed cache design in sub-0.18 /spl mu/m technologies , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).
[8] Jan M. Rabaey,et al. SRAM leakage suppression by minimizing standby supply voltage , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).
[9] M. Bohr,et al. A fully synchronized, pipelined, and re-configurable 50 Mb SRAM on 90 nm CMOS technology for logic applications , 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).