Software Radio and Dynamic Reconfiguration on a DSP/FPGA platform

This paper discusses the implementation of modulation chains for multi-standard communications on a dynamically and partially reconfigurable heterogeneous platform. Implementation results highlight the benefit of considering a DSP/FPGA platform instead of a multi-DSP platform since the FPGA supports efficiently intensive computation components, which reduces the DSP load. Furthermore, partial dynamic reconfiguration increases the overall performance as compared to total dynamic reconfiguration since there is 45% of bitstream size reduction, which leads to a 45% decrease of the whole reconfiguration time. The implementation of modulation chains for multi-standard communications proves the availability of new technology to support efficiently Software Defined Radio.

[1]  Joseph Mitola,et al.  The software radio architecture , 1995, IEEE Commun. Mag..

[2]  R. I. Lackey,et al.  Speakeasy: the military software radio , 1995, IEEE Commun. Mag..

[3]  Mike Peattie.  Two Flows for Partial Reconfiguration: Module Based or Small Bit Manipulations , 2000 .

[4]  Cameron Patterson.  A Dynamic Module Server for Embedded Platform FPGAs , 2003, Engineering of Reconfigurable Systems and Algorithms.

[5]  Hanna Bogucka,et al.  WIND-FLEX: developing a novel testbed for exploring flexible radio concepts in an indoor environment , 2003, IEEE Commun. Mag..

[6]  Reiner W. Hartenstein,et al.  A decade of reconfigurable computing: a visionary retrospective , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[7]  Philip James-Roxby,et al.  A Self-reconfiguring Platform , 2003, FPL.

[8]  Mark Cummings,et al.  FPGA in the software radio , 1999, IEEE Commun. Mag..

[9]  Jeffrey H. Reed,et al.  An overview of configurable computing machines for software radio handsets , 2003, IEEE Commun. Mag..

[10]  J. Lockwood,et al.  Dynamic hardware plugins in an FPGA with partial run-time reconfiguration , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[11]  Hiroshi Harada,et al.  Multimode Software Radio System by Parameter Controlled and Telecommunication Component Block Embedded Digital Signal Processing Hardware , 2000 .

[12]  Fernando Gehm Moraes,et al.  Remote and partial reconfiguration of FPGAs: tools and trends , 2003, Proceedings International Parallel and Distributed Processing Symposium.

[13]  Christophe Bobda,et al.  Increasing Efficiency by Partial Hardware Reconfiguration: Case Study of a Multi-Controller System , 2003, Engineering of Reconfigurable Systems and Algorithms.

[14]  Jacques Palicot,et al.  FFT: a basic function for a reconfigurable receiver , 2003, 10th International Conference on Telecommunications, 2003. ICT 2003..

[15]  I. Xilinx.  Virtex series configuration architecture user guide , 2000 .