On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits

In this paper, a new methodology is proposed to improve digital circuit signal integrity, in the presence of power-supply voltage (Vdd) and temperature (T) variations. The underlying principle of the proposed methodology is to introduce on-line additional tolerance, by dynamically controlling the instant of occurrence of the clock edge trigger driving specific memory cells. On-line, dynamic delay insertion in the clock signal driving such memory cells is performed, according to local VDD and/or T variations, using a dynamic delay buffer (DDB) block. The circuit becomes more tolerant to power line and temperature fluctuations, while maintaining at-speed clock rate. Moreover, when clock frequency reduction becomes unavoidable, the methodology improves signal integrity when the disturbances start to occur, allowing time for the clock generator to react and reduce its frequency. Experimental results based on SPICE simulations for two sequential circuits are used to demonstrate the usefulness of the proposed methodology.

[1]  Luca Benini,et al.  Clock Skew Optimization for Peak Current Reduction , 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

[2]  R. Alves.  Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test , 2005 .

[3]  K. Roy,et al.  A time borrowing selectively clocked skewed logic for high-performance circuits in scaled technologies , 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

[4]  Sandeep K. Gupta,et al.  Structural delay testing of latch-based high-speed pipelines with time borrowing , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[5]  Sonia Ben Dhia,et al.  Electromagnetic Compatibility of Integrated Circuits: Techniques for low emission and susceptibility , 2006 .

[6]  Gerald E. Sobelman,et al.  Time borrowing in high-speed functional units using skew-tolerant domino circuits , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[7]  Mark Horowitz,et al.  Timing analysis including clock skew , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Resve A. Saleh,et al.  Full-chip verification of UDSM designs , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[9]  Christopher M. Durham,et al.  High Speed CMOS Design Styles , 1998 .

[10]  Fabian Vargas.  Design and test on chip for EMC , 2006, IEEE Design & Test of Computers.

[11]  Jiang Tao,et al.  Design in hot-carrier reliability for high performance logic applications , 1998, Proceedings of the IEEE 1998 Custom Integrated Circuits Conference (Cat. No.98CH36143).

[12]  Trevor Mudge,et al.  Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[13]  L. Green.  Understanding the importance of signal integrity , 1999 .

[14]  Mehrdad Nourani,et al.  Signal Integrity: Fault Modeling and Testing in High-Speed SoCs , 2002, J. Electron. Test..

[15]  Andrew B. Kahng,et al.  Interconnect optimization strategies for high-performance VLSI designs , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

[16]  David Blaauw,et al.  Razor: circuit-level correction of timing errors for low-power operation , 2004, IEEE Micro.

[17]  João Paulo Teixeira,et al.  Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip , 2005, J. Electron. Test..

[18]  J. P. Teixeira,et al.  Digital Circuit Signal Integrity Enhancement by Monitoring Power Grid Activity , 2006 .

[19]  Sachin S. Sapatnekar,et al.  Interleaving buffer insertion and transistor sizing into a single optimization , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[20]  Thomas Steinecke,et al.  EMC modeling and simulation on chiplevel , 2001, 2001 IEEE EMC International Symposium. Symposium Record. International Symposium on Electromagnetic Compatibility (Cat. No.01CH37161).

[21]  Sujit Dey,et al.  Fault modeling and simulation for crosstalk in system-on-chip interconnects , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[22]  Majid Sarrafzadeh,et al.  Minimal buffer insertion in clock trees with skew and slew rate constraints , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[23]  L. K. Wang,et al.  Design For Signal Integrity: The New Paradigm For Deept!lubmicron Vlsi Design , 1997, Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications.

[24]  George A. Katopis,et al.  Decoupling capacitor effects on switching noise , 1992, [1992 Proceedings] Electrical Performance of Electronic Packaging.

[25]  Kaushik Roy,et al.  Estimation of switching noise on power supply lines in deep sub-micron CMOS circuits , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.