All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control

A 45 nm microprocessor integrates an all-digital dynamic variation monitor (DVM) to continuously measure the impact of dynamic parameter variations on circuit-level performance to enhance silicon debug and adaptive clock control. The DVM consists of a tunable replica circuit, a time-to-digital converter, and multiplexers to measure circuit delay or frequency changes with less than a 1% measured resolution error while capturing clock-to-data correlations. In validating the DVM with microprocessor maximum clock frequency (FMAX) measurements, an on-die noise injector circuit induces a supply voltage (VCC) droop at a particular cycle in the test program. The FMAX measurement is then repeated for over a thousand iterations while shifting the droop placement to a different cycle per iteration. Silicon measurements demonstrate the DVM capability of tracking the worst case FMAX reduction to within 1% for a wide range of VCC droop profiles. Furthermore, silicon measurements reveal that FMAX is highly sensitive to the placement and magnitude of a high-frequency VCC droop during program execution, thus highlighting the value of the DVM for silicon debug. In addition, the DVM interfaces with an adaptive clock control circuit to dynamically adjust the clock frequency by changing the divide ratio in the phase-locked loop in response to persistent variations, enabling the microprocessor to adapt to the operating environment for maximum efficiency.

[1]  Jie Gu,et al.  Circuit Design and Modeling Techniques for Enhancing the Clock-Data Compensation Effect Under Resonant Supply Noise , 2010, IEEE Journal of Solid-State Circuits.

[2]  J. Tschanz,et al.  Tunable replica circuits and adaptive voltage-frequency techniques for dynamic voltage, temperature, and aging variation tolerance , 2009, 2009 Symposium on VLSI Circuits.

[3]  Paolo A. Aseron,et al.  A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance , 2011, IEEE Journal of Solid-State Circuits.

[4]  T. Arabi,et al.  Enhanced thermal management for future processors , 2003, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

[5]  Poras T. Balsara,et al.  A wide-range, high-resolution, compact, CMOS time to digital converter , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

[6]  E. Alon,et al.  The implementation of a 2-core, multi-threaded itanium family processor , 2006, IEEE Journal of Solid-State Circuits.

[7]  Ramy E. Aly,et al.  A Family of 32 nm IA Processors , 2011, IEEE Journal of Solid-State Circuits.

[8]  R. Chau,et al.  A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging , 2007, 2007 IEEE International Electron Devices Meeting.

[9]  K.A. Bowman,et al.  Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance , 2009, IEEE Journal of Solid-State Circuits.

[10]  Doug Josephson,et al.  Voltage transient detection and induction for debug and test , 2009, 2009 International Test Conference.

[11]  Paolo A. Aseron,et al.  Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency , 2010, IEEE Custom Integrated Circuits Conference 2010.

[12]  M. Horowitz,et al.  Circuits and techniques for high-resolution measurement of on-chip power supply noise , 2004, IEEE Journal of Solid-State Circuits.

[13]  T. Rahal-Arabi,et al.  Enhancing microprocessor immunity to power supply noise with clock-data compensation , 2006, IEEE Journal of Solid-State Circuits.

[14]  S. Naffziger,et al.  A 90-nm variable frequency clock system for a power-managed itanium architecture processor , 2006, IEEE Journal of Solid-State Circuits.

[15]  S. Naffziger,et al.  Power and temperature control on a 90-nm Itanium family processor , 2006, IEEE Journal of Solid-State Circuits.

[16]  Greg Taylor,et al.  Temperature Sensor Design in a High Volume Manufacturing 65nm CMOS Digital Process , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[17]  T. Rahal-Arabi,et al.  On-die droop detector for analog sensing of power supply noise , 2004, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408).

[18]  Soraya Ghiasi,et al.  A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[19]  Saurabh Dighe,et al.  Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[20]  Ching-Che Chung,et al.  An Autocalibrated All-Digital Temperature Sensor for On-Chip Thermal Monitoring , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[21]  N. Kurd,et al.  Next Generation Intel¯ Core™ Micro-Architecture (Nehalem) Clocking , 2009, IEEE Journal of Solid-State Circuits.

[22]  Poki Chen,et al.  All-Digital Time-Domain Smart Temperature Sensor With an Inter-Batch Inaccuracy of $-{\hbox {0.7}} ~^{\circ}{\hbox {C}}-+{\hbox {0.6}}~^{\circ}{\hbox {C}}$ After One-Point Calibration , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.