The design and optimization of the high-speed digital subscriber line (HDSL) need powerful computational strategies. Traditional techniques of distributing poles and zeros on Smith charts generally do not work. In the past, such approaches have lead to suboptimal designs for applications where the data capacity sought is considerably less than the Shanon capacity of the lines. Typical subscriber loops are less than perfect and for the current demands on the HDSL at T1/T2 and E1 rates every possible venue for the HDSL design need to be investigated, if not exploited. The authors present flexible computational techniques that explore and optimize system components in view of operating environment of the HDSL and/or the asymmetric digital subscriber line (ADSL), and the inherent limitations of the system components. The optimization occurs automatically by forcing the computer to track the effects of incremental changes of the subsystem performance (e.g. echo cancelers or equalizers), or the component values (R's and C's in the matching circuits) in context of the functional constraints of the line (HDSL, ADSL, duplex, dual-duplex, triplex, etc.) in conjunction with the subscriber loop (CSA, Loops <18 kft., American, Australian, European, ANSI, ETSI, etc.) environments.<<ETX>>
[1]
B. Bosik,et al.
A Time Compression Multiplexing System for a Circuit Switched Digital Capability
,
1982,
IEEE Trans. Commun..
[2]
George S. Moschytz,et al.
Transhybrid Loss with RC Balance Circuits for Primary-Rate ISDN Transmission Systems
,
1991,
IEEE J. Sel. Areas Commun..
[3]
W. A. Griffin,et al.
Design of an integrated circuit for the T1C low-power line repeater
,
1979
.
[4]
S. V. Ahamed,et al.
Simulation and design studies of digital subscriber lines
,
1982,
The Bell System Technical Journal.
[5]
S. Ahamed,et al.
A Tutorial on Two-Wire Digital Transmission in the Loop Plant
,
1981,
IEEE Transactions on Communications.
[6]
R. A. Tarbox.
An automatic equalizer for digital repeatered lines
,
1969
.