Application of logical effort techniques for speed optimization and analysis of representative adders

This paper presents the transistor-level analysis of contemporary 64-bit adders. The logical effort technique is applied to provide more descriptive presentation of the delay and circuit architecture. It also enables optimization of gate size for optimal performance. The selected adders are dynamic carry-lookahead adder (DCLA), static carry-select adder (SCSA), dynamic Kogge-Stone adder (DKSA) and Ling/conditional-sum adder (DLCNSA). The results match well with simulation using 0.18 /spl mu/m, 1.8 V CMOS. Adders with fewer levels in the critical path show superior performance. In particular, for dynamic adders, a 0.6-FO4 per-gate delay improvement was observed.

[1]  G. G. Stokes.  "J." , 1890, The New Yale Book of Quotations.

[2]  Vojin G. Oklobdzija,et al.  Multiplexer based adder for media signal processing , 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).

[3]  Jaehong Park,et al.  470ps 64bit Parallel Binary Adder , 2000 .

[4]  Vojin G. Oklobdzija,et al.  Improved CLA scheme with optimized delay , 1991, J. VLSI Signal Process..

[5]  S.H. Dhong,et al.  470 ps 64-bit parallel binary adder [for CPU chip] , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[6]  V.G. Oklobdzija,et al.  Application of logical effort on design of arithmetic blocks , 2001, Conference Record of Thirty-Fifth Asilomar Conference on Signals, Systems and Computers (Cat.No.01CH37256).