Hybrid integrated Si nanosheet GAA-FET and stacked SiGe/Si FinFET using selective channel release strategy

[1]  C. Liu,et al.  Experimental Demonstration of TreeFETs Combining Stacked Nanosheets and Low Doping Interbridges by Epitaxy and Wet Etching , 2022, IEEE Electron Device Letters.

[2]  Jun Luo,et al.  Four-Period Vertically Stacked SiGe/Si Channel FinFET Fabrication and Its Electrical Characteristics , 2021, Nanomaterials.

[3]  F. Andrieu,et al.  7-Levels-Stacked Nanosheet GAA Transistors for High Performance Computing , 2020, 2020 IEEE Symposium on VLSI Technology.

[4]  Qinghua Li,et al.  Investigation and optimization of electrical and thermal performance for 5-nm GAA vertically stacked nanowire FETs , 2020, Microelectron. J..

[5]  Jun He,et al.  5nm CMOS Production Technology Platform featuring full-fledged EUV, and High Mobility Channel FinFETs with densest 0.021µm2 SRAM cells for Mobile SoC and High Performance Computing Applications , 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

[6]  M. Belyansky,et al.  A Novel Dry Selective Etch of SiGe for the Enablement of High Performance Logic Stacked Gate-All-Around NanoSheet Devices , 2019, 2019 IEEE International Electron Devices Meeting (IEDM).

[7]  Y. Oniki,et al.  (Invited) Selective Etches for Gate-All-Around (GAA) Device Integration: Opportunities and Challenges , 2019, ECS Transactions.

[8]  S. Jung,et al.  3nm GAA Technology featuring Multi-Bridge-Channel FET for Low Power and High Performance Applications , 2018, 2018 IEEE International Electron Devices Meeting (IEDM).

[9]  J. G. Lee,et al.  Impact of aggressive fin width scaling on FinFET device characteristics , 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

[10]  D. Mocuta,et al.  Vertically stacked gate-all-around Si nanowire transistors: Key Process Optimizations and Ring Oscillator Demonstration , 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

[11]  D. Corliss,et al.  Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET , 2017, 2017 Symposium on VLSI Technology.

[12]  Jongwook Jeon,et al.  A novel tensile Si (n) and compressive SiGe (p) dual-channel CMOS FinFET co-integration scheme for 5nm logic applications and beyond , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[13]  Shahriar Mirabbasi,et al.  System-on-Chip: Reuse and Integration , 2006, Proceedings of the IEEE.

[14]  D. Paul.  Si/SiGe heterostructures: from material and physics to devices and circuits , 2004 .

[15]  Antonio J. García-Loureiro,et al.  Benchmarking of FinFET, Nanosheet, and Nanowire FET Architectures for Future Technology Nodes , 2020, IEEE Access.