High-level Power Modeling, Estimation, And Optimization

In the past, the major concerns of the VLSI designers were area, performance, cost, and reliability. I n recent years, however, this has changed and, increasingly, power is being given comparable weight t o area and speed. Th i s is mainly due to the remarkable success of personal computing devices and wireless communicat ion systems, which demand high-speed computat ion and complex funct ional i ty with low power consumption. I n addition, there exists a strong pressure f o r manufacturers of high-end products to keep power under control. T h e m a i n driving factors f o r lower power dissipation in these products are the costs associated with packaging and cooling, and circuit reliability. Tools f o r the automatic design of low-power VLSI systems have thus become mandatory. More specifically, following a natural trend, interests of researchers have lately shifted to the investigation of high-level power modeling, es t imation, synthesis, and opt imizat ion techniques tha t account f o r power dissipation as the pr imary cost factor. Th i s paper provides a non-exhaustive survey of the most successful and innovat ive ideas in this area that have appeared i n the literature in the last f e w years.

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