Machine Learning for Electronic Design Automation: A Survey

With the down-scaling of CMOS technology, the design complexity of very large-scale integrated is increasing. Although the application of machine learning (ML) techniques in electronic design automation (EDA) can trace its history back to the 1990s, the recent breakthrough of ML and the increasing complexity of EDA tasks have aroused more interest in incorporating ML to solve EDA tasks. In this article, we present a comprehensive review of existing ML for EDA studies, organized following the EDA hierarchy.

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[2]  Bei Yu,et al.  Efficient Layout Hotspot Detection via Binarized Residual Neural Network Ensemble , 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Jiaqi Gu,et al.  DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement , 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Zhiru Zhang,et al.  Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural Networks , 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

[5]  Bei Yu,et al.  Hotspot Detection via Attention-based Deep Layout Metric Learning , 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

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[7]  Yanqing Zhang,et al.  Opportunities for RTL and Gate Level Simulation using GPUs (Invited Talk) , 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

[8]  Tsung-Wei Huang,et al.  A General-purpose Parallel and Heterogeneous Task Programming System for VLSI CAD , 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

[9]  Evangeline F. Y. Young,et al.  PROS: A Plug-in for Routability Optimization applied in the State-of-the-art commercial EDA tool using deep learning , 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

[10]  Chen Zhao,et al.  Empyrean ALPS-GT: GPU-accelerated Analog Circuit Simulation , 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

[11]  Han Zhou,et al.  GridNet: Fast Data-Driven EM-Induced IR Drop Prediction and Localized Fixing for On-Chip Power Grid Networks* , 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

[12]  Yiran Chen,et al.  Routing-Free Crosstalk Prediction , 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

[13]  Sung Kyu Lim,et al.  VLSI Placement Parameter Optimization using Deep Reinforcement Learning , 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

[14]  Evangeline F. Y. Young,et al.  Neural-ILT: Migrating ILT to Neural Networks for Mask Printability and Complexity Co-optimization , 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

[15]  Bei Yu,et al.  Learn to Floorplan through Acquisition of Effective Local Search Heuristics , 2020, 2020 IEEE 38th International Conference on Computer Design (ICCD).

[16]  Sachin S. Sapatnekar,et al.  A general approach for identifying hierarchical symmetry constraints for analog circuit layout , 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

[17]  Bei Yu,et al.  DAMO: Deep Agile Mask Optimization for Full Chip Scale , 2020, 2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD).

[18]  Zi Wang,et al.  Machine Leaming to Set Meta-Heuristic Specific Parameters for High-Level Synthesis Design Space Exploration , 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

[19]  Sung Kyu Lim,et al.  TP-GNN: A Graph Neural Network Framework for Tier Partitioning in Monolithic 3D ICs , 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

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[22]  Walker J. Turner,et al.  ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks , 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

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[25]  Yayi Wei,et al.  Semisupervised Hotspot Detection With Self-Paced Multitask Learning , 2020, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[26]  Song Han,et al.  GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning , 2020, 2020 57th ACM/IEEE Design Automation Conference (DAC).

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[30]  Sachin S. Sapatnekar,et al.  GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits , 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[31]  Hongxiang Fan,et al.  Improving Performance Estimation for FPGA-Based Accelerators for Convolutional Neural Networks , 2020, ARC.

[32]  B. Nikolić,et al.  AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs , 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

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[34]  Nan Sun,et al.  S3DET: Detecting System Symmetry Constraints for Analog Circuits with Graph Similarity , 2020, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

[35]  Yiran Chen,et al.  FIST: A Feature-Importance Sampling and Tree-Based Method for Automatic Design Flow Parameter Tuning , 2020, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

[36]  Yiran Chen,et al.  PowerNet: Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network , 2020, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

[37]  Sachin S. Sapatnekar,et al.  Template-based PDN Synthesis in Floorplan and Placement Using Classifier and CNN Techniques , 2020, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

[38]  Wei Zhong,et al.  VLSI Mask Optimization: From Shallow To Deep Learning , 2019, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

[39]  Mohamed Shalan,et al.  DRiLLS: Deep Reinforcement Learning for Logic Synthesis , 2019, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).

[40]  Michael Rotman,et al.  Electric Analog Circuit Design with Hypernetworks And A Differential Simulator , 2019, ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).

[41]  Joydeep Mitra,et al.  SRAF Insertion via Supervised Dictionary Learning , 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[42]  Natalia Gimelshein,et al.  PyTorch: An Imperative Style, High-Performance Deep Learning Library , 2019, NeurIPS.

[43]  R. D. Blanton,et al.  Improving Test Chip Design Efficiency via Machine Learning , 2019, 2019 IEEE International Test Conference (ITC).

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[45]  Nan Sun,et al.  GeniusRoute: A New Analog Routing Paradigm Using Generative Neural Network Guidance , 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[46]  Pierre-Emmanuel Gaillardon,et al.  LSOracle: a Logic Synthesis Framework Driven by Artificial Intelligence: Invited Paper , 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[47]  Andrew B. Kahng,et al.  IncPIRD: Fast Learning-Based Prediction of Incremental IR Drop , 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[48]  Jerry Zhao,et al.  Simmani: Runtime Power Modeling for Arbitrary RTL with Automatic Signal Selection , 2019, MICRO.

[49]  Andrew B. Kahng,et al.  RePlAce: Advancing Solution Quality and Routability Validation in Global Placement , 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[50]  Liang Zhao,et al.  Pyramid: Machine Learning Framework to Estimate the Optimal Timing and Resource Usage of a High-Level Synthesis Design , 2019, 2019 29th International Conference on Field Programmable Logic and Applications (FPL).

[51]  Vladimir Stojanovic,et al.  BagNet: Berkeley Analog Generator with Layout Optimizer Boosted with Deep Neural Networks , 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[52]  Xuan Zeng,et al.  Faster Region-based Hotspot Detection , 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

[53]  Luca P. Carloni,et al.  A Learning-Based Recommender System for Autotuning Design FIows of Industrial High-Performance Processors , 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

[54]  Yiran Chen,et al.  Machine Learning-Based Pre-Routing Timing Prediction with Reduced Pessimism , 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

[55]  Nan Sun,et al.  WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit Layout , 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

[56]  Yuan Zhou,et al.  PRIMAL: Power Inference using Machine Learning , 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

[57]  Brucek Khailany,et al.  High Performance Graph ConvolutionaI Networks with Applications in Testability Analysis , 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

[58]  Po-Cheng Pan,et al.  Late Breaking Results: An Efficient Learning-based Approach for Performance Exploration on Analog and RF Circuit Synthesis , 2019, 2019 56th ACM/IEEE Design Automation Conference (DAC).

[59]  Dina Katabi,et al.  Circuit-GNN: Graph Neural Networks for Distributed Circuit Design , 2019, ICML.

[60]  Daijoon Hyun,et al.  Accurate Wirelength Prediction for Placement-Aware Synthesis through Machine Learning , 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[61]  Nikolaj Bjørner,et al.  Guiding High-Performance SAT Solvers with Unsat-Core Predictions , 2019, SAT.

[62]  Jieru Zhao,et al.  Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis , 2019, 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[63]  Avesta Sasan,et al.  XPPE: cross-platform performance estimation of hardware accelerators using machine learning , 2019, ASP-DAC.

[64]  Ya-Chieh Lai,et al.  Detecting multi-layer layout hotspots with adaptive squish patterns , 2019, ASP-DAC.

[65]  Andrew B. Kahng,et al.  Learning-based prediction of package power delivery network quality , 2019, ASP-DAC.

[66]  Markus Weimer,et al.  Learning To Solve Circuit-SAT: An Unsupervised Differentiable Approach , 2018, ICLR.

[67]  Yuzhe Ma,et al.  Cross-Layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[68]  David L. Dill,et al.  Learning a SAT Solver from Single-Bit Supervision , 2018, ICLR.

[69]  Wei Ye,et al.  LithoGAN : End-to-End Lithography Modeling with Generative Adversarial Networks , 2019 .

[70]  Nuno Horta,et al.  Using ANNs to Size Analog Integrated Circuits , 2019 .

[71]  Barnabás Póczos,et al.  Learning Local Search Heuristics for Boolean Satisfiability , 2019, NeurIPS.

[72]  Song Han,et al.  Learning to Design Circuits , 2018, ArXiv.

[73]  Partha Pratim Pande,et al.  Machine Learning for Design Space Exploration and Optimization of Manycore Systems , 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[74]  Yiran Chen,et al.  RouteNet: Routability prediction for Mixed-Size Designs Using Convolutional Neural Network , 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[75]  Philip Brisk,et al.  HLSPredict: Cross Platform Performance Prediction for FPGA High-Level Synthesis , 2018, 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[76]  Nobukazu Takai,et al.  Inference of Suitable for Required Specification Analog Circuit Topology using Deep Learning , 2018, 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS).

[77]  Sanjit A. Seshia,et al.  Learning Heuristics for Automated Reasoning through Deep Reinforcement Learning , 2018, ArXiv.

[78]  Gary William Grewal,et al.  Machine-Learning Based Congestion Estimation for Modern FPGAs , 2018, 2018 28th International Conference on Field Programmable Logic and Applications (FPL).

[79]  Nima Tajbakhsh,et al.  UNet++: A Nested U-Net Architecture for Medical Image Segmentation , 2018, DLMIA/ML-CDS@MICCAI.

[80]  Yuzhe Ma,et al.  GAN-OPC: Mask Optimization with Lithography-guided Generative Adversarial Nets , 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

[81]  Ya Wang,et al.  HFMV: Hybridizing Formal Methods and Machine Learning for Verification of Analog and Mixed-Signal Circuits , 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

[82]  Shahin Nazarian,et al.  Accelerating Coverage Directed Test Generation for Functional Verification: A Neural Network-based Framework , 2018, ACM Great Lakes Symposium on VLSI.

[83]  Giovanni De Micheli,et al.  Deep Learning for Logic Optimization Algorithms , 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

[84]  Wei-Kai Cheng,et al.  Evaluation of routability-driven macro placement with machine-learning technique , 2018, 2018 7th International Symposium on Next Generation Electronics (ISNE).

[85]  Giovanni De Micheli,et al.  Developing Synthesis Flows Without Human Knowledge , 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

[86]  Evangeline F. Y. Young,et al.  Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning , 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

[87]  Sung Kyu Lim,et al.  Compact-2D: A Physical Design Methodology to Build Commercial-Quality Face-to-Face-Bonded 3D ICs , 2018, ISPD.

[88]  Zhijian Pan,et al.  Low-cost high-accuracy variation characterization for nanoscale IC technologies via novel learning-based techniques , 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[89]  Andreas Gerstlauer,et al.  Learning-Based, Fine-Grain Power Modeling of System-Level Hardware IPs , 2018, ACM Trans. Design Autom. Electr. Syst..

[90]  Yuan Zhou,et al.  Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs , 2018, FPGA.

[91]  Richard Evans,et al.  Can Neural Networks Understand Logical Entailment? , 2018, ICLR.

[92]  Andrew B. Kahng,et al.  New directions for learning-based IC design tools and methodologies , 2018, 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC).

[93]  Ole Winther,et al.  Recurrent Relational Networks for Complex Relational Reasoning , 2018, ArXiv.

[94]  Kris Gaj,et al.  Minerva: Automated hardware optimization tool , 2017, 2017 International Conference on ReConFigurable Computing and FPGAs (ReConFig).

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[98]  Di Gao,et al.  Accelerating chip design with machine learning: From pre-silicon to post-silicon , 2017, 2017 30th IEEE International System-on-Chip Conference (SOCC).

[99]  Krzysztof Czarnecki,et al.  An Empirical Study of Branching Heuristics Through the Lens of Global Learning Rate , 2017, SAT.

[100]  Chenxi Lin,et al.  Imbalance aware lithography hotspot detection: a deep learning approach , 2017 .

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[102]  Evangeline F. Y. Young,et al.  Layout hotspot detection with feature tensor generation and deep biased learning , 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).

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[110]  Paul D. Franzon,et al.  Machine learning in physical design , 2016, 2016 IEEE 25th Conference on Electrical Performance Of Electronic Packaging And Systems (EPEPS).

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[112]  Dong Liu,et al.  Efficient and reliable High-Level Synthesis Design Space Explorer for FPGAs , 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

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[117]  Pingfan Meng,et al.  Adaptive Threshold Non-Pareto Elimination: Re-thinking machine learning for system level design space exploration on FPGAs , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[118]  Alex Doboli,et al.  Analog circuit topological feature extraction with unsupervised learning of new sub-structures , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[119]  Andrew B. Kahng,et al.  Learning-based prediction of embedded memory timing failures during initial floorplan design , 2016, 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC).

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