Design and measurement of an inductance-oscillator for analyzing inductance impact on on-chip interconnect delay

A newly devised inductance-oscillator (iOSC) has been developed which evaluates inductance impact on on-chip interconnect delay. iOSC is a ring oscillator which is comprised of a set of wires each with different loop inductance and accurate on-chip counter. The equivalent distance to the nearest ground grid, which serves as the current return path, is varied to control wire inductance. A test chip using 0.13 /spl mu/m node process is fabricated to demonstrate the concept of the iOSC. Four interconnect structures are implemented as imperfect coplanar waveguide, imitating clock lines or high-frequency inter-module signal lines. The structure with largest inductance variation measured 99 ps while a twisted ground structure which has small inductance variation measured 6 ps both for 3-mm wires. The experiments confirm that the inductance impact on delay has to be adequately analyzed and controlled to estimate a timing of budget in high-speed LSI designs.