Synthesis techniques for CMOS folded source-coupled logic circuits

The application of series-gated, multiplexer-minimization, and variable-entered mapping methods to the synthesis of fully differential CMOS folded source-coupled logic (FSCL) gates is described. In contrast to conventional static logic, FSCL dissipates DC power. Its total power consumption is competitive at higher speeds where its low digital switching noise is most advantageous. The minimum propagation delay of a simple FSCL gate compares favorably to a conventional gate. Complex functions are generally faster in FSCL since its fully differential topology requires fewer stages of delay. Simulated and measured results are presented for several combinational and sequential FSCL gates in a 2- mu m p-well CMOS process. With V/sub dd/=5 V, a FSCL (static) inverter achieved a minimum propagation delay of 400 ps (350 ps) with a power-delay product of 0.5 pJ (0.3 pJ); a FSCL (static) 1-b full adder achieved a minimum delay of 3.0 ns (12.0 ns) with a power-delay product of 0.3 pJ (11.0 pJ). >

[1]  San-hwa Chee,et al.  CMOS differential logic techniques for mixed-mode applications , 1990 .

[2]  Eric A. Vittoz The Design of High-Performance Analog Circuits on Digital CMOS Chips , 1985 .

[3]  George H. Warren,et al.  NOISE, CROSSTALK AND DISTORTION IN MIXED ANALOGlDIGITAL INTEGRATED , 1988 .

[4]  D.A. Hodges,et al.  A self-calibrating 15 bit CMOS A/D converter , 1984, IEEE Journal of Solid-State Circuits.

[5]  James C. Candy,et al.  Decimation for Sigma Delta Modulation , 1986, IEEE Trans. Commun..

[6]  E. Swanson,et al.  A monolithic 20 b delta-sigma A/D converter , 1990, 1990 37th IEEE International Conference on Solid-State Circuits.

[7]  David J. Allstot,et al.  A substrate-referenced data-conversion architecture , 1991 .

[8]  David L. Pulfrey,et al.  A comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logic , 1987 .

[9]  William I. Fletcher Engineering approach to digital design , 1980 .

[10]  Sayfe Kiaei,et al.  CMOS source-coupled logic for mixed-mode VLSI , 1990, IEEE International Symposium on Circuits and Systems.

[11]  Richard F. Lyon,et al.  Two's Complement Pipeline Multipliers , 1976, IEEE Trans. Commun..

[12]  J. Kane A low-power, bipolar, two's complement serial pipeline multiplier chip , 1976, IEEE Journal of Solid-State Circuits.

[13]  B.M.J. Kup,et al.  A bit-stream digital-to-analog converter with 18-b resolution , 1991 .

[14]  Bedrich J. Hosticka,et al.  The art of analog circuit design in a digital VLSI world , 1990, IEEE International Symposium on Circuits and Systems.

[15]  Claude E. Shannon,et al.  A symbolic analysis of relay and switching circuits , 1938, Transactions of the American Institute of Electrical Engineers.

[16]  P. L. Jones,et al.  Minimisation technique for series-gated emitter-coupled logic , 1989 .

[17]  G. H. Warren,et al.  Noise, crosstalk and distortion in mixed analog/digital integrated circuits , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

[18]  David L. Pulfrey,et al.  Design procedures for differential cascode voltage switch circuits , 1986 .

[19]  Aihua Li,et al.  VLSI design of multi-rate arrays for DSP algorithm , 1990, International Conference on Acoustics, Speech, and Signal Processing.