Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module

This work describes the circuit and physical design implementation of the processor chip (CP), level-4 cache chip (SC), and the multi-chip module at the heart of the EC12 system. The chips were implemented in IBM's high-performance 32nm high-k/metal-gate SOI technology. The CP chip contains 6 super-scalar, out-of-order processor cores, running at 5.5 GHz, while the SC chip contains 192 MB of eDRAM cache. Six CP chips and two SC chips are mounted on a high-performance glass-ceramic substrate, which provides high-bandwidth, low-latency interconnections. Various aspects of the design are explored in detail, with most of the focus on the CP chip, including the circuit design implementation, clocking, thermal modeling, reliability, frequency tuning, and comparison to the previous design in 45nm technology.

[1]  M. Belyansky,et al.  High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm2 SRAM and ultra low-k back end with eleven levels of copper , 2006, 2009 Symposium on VLSI Technology.

[2]  John Davis,et al.  7GHz L1 cache SRAMs for the 32nm zEnterprise™ EC12 processor , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[3]  V. Zyuban,et al.  POWER7TM local clocking and clocked storage elements , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[4]  Chung-Lung Kevin Shum,et al.  5.5GHz system z microprocessor and multi-chip module , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[5]  Haifeng Qian,et al.  Subtractive Router for Tree-Driven-Grid Clocks , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Eric M. Schwarz,et al.  The zEnterprise 196 System and Microprocessor , 2011, IEEE Micro.

[7]  William V. Huott,et al.  On-chip Timing Uncertainty Measurements on IBM Microprocessors , 2008, 2008 IEEE International Test Conference.

[8]  Ting-Yen Chiang,et al.  Impact of Joule Heating on Deep SubMicron Cu / low-k Interconnects , 2004 .

[9]  D. Badami,et al.  A robust reliability methodology for accurately predicting Bias Temperature Instability induced circuit performance degradation in HKMG CMOS , 2011, 2011 International Reliability Physics Symposium.

[10]  T. Kirihata,et al.  A 0.039um2 high performance eDRAM cell based on 32nm High-K/Metal SOI technology , 2010, 2010 International Electron Devices Meeting.

[11]  John Davis,et al.  Circuit and Physical Design Implementation of the Microprocessor Chip for the zEnterprise System , 2012, IEEE Journal of Solid-State Circuits.

[12]  Baozhen Li,et al.  Statistical Evaluation of Electromigration Reliability at Chip Level , 2011, IEEE Transactions on Device and Materials Reliability.

[13]  Andreas Huber,et al.  Electronic packaging of the IBM System z196 enterprise-class server processor cage , 2012, IBM J. Res. Dev..

[14]  Fadi Busaba,et al.  IBM zEC12: The Third-Generation High-Frequency Mainframe Microprocessor , 2013, IEEE Micro.