EXPLORATION TOWARDS ELECTROSTATIC INTEGRITY FOR SIGE ON INSULATOR (SG-OI) ON JUNCTIONLESS CHANNEL TRANSISTOR (JLCT)

In view of reduced electric field and avoiding source drain engineering, the work exploresstrain effect in junctionless channel transistor. To achieve scaled I OFF and maintain I ON, here the device SG-OI JLCT is proposed. The study discusses higher switching action with mole fraction x = 0.25. The dependency of ϕ M and the N D is responsible for maintaining constant current for overall analysis.

[1]  A. Kranti,et al.  Junctionless nanowire transistor (JNT): Properties and design guidelines , 2010, 2010 Proceedings of the European Solid State Device Research Conference.

[2]  L. Hitt,et al.  p-channel germanium MOSFETs with high channel mobility , 1989, IEEE Electron Device Letters.

[3]  S. K. Mohapatra,et al.  Some Device Design Considerations to Enhance the Performance of DG-MOSFETs , 2013 .

[4]  S. Kundu,et al.  Simulation to Study the Effect of Oxide Thickness and High-$K$ Dielectric on Drain-Induced Barrier Lowering in N-type MOSFET , 2013, IEEE Transactions on Nanotechnology.

[5]  F. Balestra,et al.  Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance , 1987, IEEE Electron Device Letters.

[6]  Abhinav Kranti,et al.  Junctionless Nanowire Transistor: Complementary Metal-Oxide-Semiconductor Without Junctions , 2011 .

[7]  Geert Hellings,et al.  Germanium MOSFET Devices: Advances in Materials Understanding, Process Development, and Electrical Performance , 2008 .

[8]  Chi-Woo Lee,et al.  Nanowire transistors without junctions. , 2010, Nature nanotechnology.

[9]  T. Kenny,et al.  What is the Young's Modulus of Silicon? , 2010, Journal of Microelectromechanical Systems.

[10]  Cor Claeys,et al.  Behavior of triple gate Bulk FinFETs with and without DTMOS operation , 2011, Ulis 2011 Ultimate Integration on Silicon.

[11]  J. Colinge,et al.  Silicon-on-insulator 'gate-all-around device' , 1990, International Technical Digest on Electron Devices.

[12]  T. Tezuka,et al.  Physical Understanding of Strain-Induced Modulation of Gate Oxide Reliability in MOSFETs , 2008, IEEE Transactions on Electron Devices.

[13]  S. Ganguly,et al.  Effect of Band-to-Band Tunneling on Junctionless Transistors , 2012, IEEE Transactions on Electron Devices.

[14]  K. Mistry,et al.  The High-k Solution , 2007, IEEE Spectrum.

[15]  C. K. Maiti,et al.  Applications of Silicon-Germanium Heterostructure Devices , 2001 .

[16]  Reliability analysis of charge plasma based double material gate oxide (DMGO) SiGe-on-insulator (SGOI) MOSFET , 2015 .

[17]  Jean-Pierre Colinge,et al.  Performance estimation of junctionless multigate transistors , 2010 .

[18]  Changhwan Shin,et al.  Design Optimization of Multigate Bulk MOSFETs , 2013, IEEE Transactions on Electron Devices.

[19]  J.-P. Colinge,et al.  The New Generation of SOI MOSFETs , 2008 .

[20]  T. Ma,et al.  Effect of Al inclusion in HfO2 on the physical and electrical properties of the dielectrics , 2002, IEEE Electron Device Letters.

[21]  Hadis Morkoç,et al.  High-κ dielectrics and advanced channel concepts for Si MOSFET , 2008 .

[22]  S. Thompson,et al.  Physics of strain effects in semiconductors and metal-oxide-semiconductor field-effect transistors , 2007 .

[23]  Chi-Woo Lee,et al.  Junctionless multigate field-effect transistor , 2009 .

[24]  Saibal Mukhopadhyay,et al.  Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits , 2003, Proc. IEEE.

[25]  Design and simulation of strained-Si/strained-SiGe dual channel hetero-structure MOSFETs , 2007 .

[26]  S. Ganguly,et al.  Bulk Planar Junctionless Transistor (BPJLT): An Attractive Device Alternative for Scaling , 2011, IEEE Electron Device Letters.