An 802.11 a/b/g/n digital fractional-N PLL with automatic TDC linearity calibration for spur cancellation

This work presents a 1.9~5.6 GHz fractional-N DPLL with digi-phase spur canceller. It utilizes a ramp signal generated from the fractional-N accumulator to automatically calibrate the TDC linearity. The chip also includes an MMD that overcomes the division ration skipping problem associated with the prior art MMDs. The ADPLL achieves a worst fractional spur level of -55 dBc and an in-band phase noise of -109 dBc/Hz (0.63 ps integrated jitter) while consuming 9.9 mW.

[1]  Giovanni Marzin,et al.  A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With −36 dB EVM at 5 mW Power , 2012, IEEE Journal of Solid-State Circuits.

[2]  F. Dai,et al.  A Multiband Fractional-N Frequency Synthesizer for a MIMO WLAN Transceiver RFIC , 2005 .

[3]  Tadashi Maeda,et al.  A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter , 2010, IEEE Journal of Solid-State Circuits.

[4]  E. Klumperink,et al.  A 12GHz 210fs 6mW digital PLL with sub-sampling binary phase detector and voltage-time modulated DCO , 2013, 2013 Symposium on VLSI Circuits.

[5]  Li Lin,et al.  9.4 A 28nm CMOS digital fractional-N PLL with −245.5dB FOM and a frequency tripler for 802.11abgn/ac radio , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[6]  Howard C. Luong,et al.  A CMOS WCDMA/WLAN Digital Polar Transmitter With AM Replica Feedback Linearization , 2013, IEEE Journal of Solid-State Circuits.

[7]  Akira Matsuzawa,et al.  A 0.84ps-LSB 2.47mW time-to-digital converter using charge pump and SAR-ADC , 2013, Proceedings of the IEEE 2013 Custom Integrated Circuits Conference.

[8]  Matthew Z. Straayer,et al.  A Low-Noise, Wide-BW 3.6GHz Digital ΔΣ Fractional-N Frequency Synthesizer with a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[9]  Foster F. Dai,et al.  A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 $\mu{\hbox {m}}$ CMOS Technology , 2010, IEEE Journal of Solid-State Circuits.

[10]  Kenichi Okada,et al.  A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique , 2015, IEEE Journal of Solid-State Circuits.

[11]  Antonio Liscidini,et al.  Time to digital converter based on a 2-dimensions Vernier architecture , 2009, 2009 IEEE Custom Integrated Circuits Conference.

[12]  Salvatore Levantino,et al.  A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation , 2011, IEEE Journal of Solid-State Circuits.

[13]  P. Dudek,et al.  A high-resolution CMOS time-to-digital converter utilizing a Vernier delay line , 2000, IEEE Journal of Solid-State Circuits.

[14]  A. Abidi,et al.  A low noise, wideband digital phase-locked loop based on a new time-to-digital converter with subpicosecond resolution , 2008, 2008 IEEE Symposium on VLSI Circuits.

[15]  C.S. Vaucher,et al.  A family of low-power truly modular programmable dividers in standard 0.35-/spl mu/m CMOS technology , 2000, IEEE Journal of Solid-State Circuits.

[16]  Michiel Steyaert,et al.  A 0.1-5GHz dual-VCO software-defined sigma delta frequency synthesizer in 45nm digital CMOS , 2009, RFIC 2009.

[17]  Giovanni Marzin,et al.  A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power , 2011, 2011 IEEE International Solid-State Circuits Conference.

[18]  Kenichi Okada,et al.  A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB , 2016, IEEE Journal of Solid-State Circuits.

[19]  F.F. Dai,et al.  A multiband /spl Delta//spl Sigma/ fractional-N frequency synthesizer for a MIMO WLAN transceiver RFIC , 2005, IEEE Journal of Solid-State Circuits.

[20]  Fa Foster Dai,et al.  A 12-bit vernier ring time-to-digital converter in 0.13μm CMOS technology , 2009, 2009 Symposium on VLSI Circuits.

[21]  Jonathan Borremans,et al.  A 86 MHz–12 GHz Digital-Intensive PLL for Software-Defined Radios, Using a 6 fJ/Step TDC in 40 nm Digital CMOS , 2010, IEEE Journal of Solid-State Circuits.

[22]  Roc Berenguer,et al.  An 802.11 a/b/g/n digital fractional-N PLL with automatic TDC linearity calibration for spur cancellation , 2016, RFIC 2016.

[23]  Matthew Z. Straayer,et al.  A Low-Noise Wide-BW 3.6-GHz Digital $\Delta\Sigma$ Fractional-N Frequency Synthesizer With a Noise-Shaping Time-to-Digital Converter and Quantization Noise Cancellation , 2008, IEEE Journal of Solid-State Circuits.

[24]  M.Z. Straayer,et al.  A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping , 2009, IEEE Journal of Solid-State Circuits.

[25]  Ahmed Elkholy,et al.  A 3.7 mW Low-Noise Wide-Bandwidth 4.5 GHz Digital Fractional-N PLL Using Time Amplifier-Based TDC , 2015, IEEE Journal of Solid-State Circuits.

[26]  Michiel Steyaert,et al.  A 0.1–5GHz Dual-VCO software-defined ∑Δ frequency synthesizer in 45nm digital CMOS , 2009, 2009 IEEE Radio Frequency Integrated Circuits Symposium.