Efficient Hotspot Thermal Simulation Via Low-Rank Model Order Reduction

Efficient full-chip thermal simulation is among the most challenging problems facing the EDA industry today, due to the need for solution of very large systems of equations that require unreasonably long computational times. However, in most cases, temperature is not required to be computed at every point of the IC but only at certain hotspots, in order to assess the circuits compliance with thermal specifications. This makes the thermal analysis problem amenable to Model Order Reduction (MOR) techniques. System-theoretic techniques like Balanced Truncation (BT) offer very reliable bounds for the approximation error, which can be used to control the order and accuracy of the reduced models during creation, at the expense of greater computational complexity to create them. In this paper, we propose a computationally efficient low-rank BT algorithm that retains all the system-theoretic advantages in the reduction of model order for fast hotspot thermal simulation. Experimental results demonstrate a 39X order reduction and very tight accuracy bounds.