Exploring optimal back bias voltages for ultra low voltage CMOS digital Circuits in 22 nm FDSOI Technology

This study presents a strategy to determine optimal body bias voltages for ultra low voltage digital circuits in the 22 nm Fully Depleted Silicon On Insulator Technology (FDSOI). The efficiency of body biasing for achieving high functional yield has been investigated by using reverse back bias voltages for HVT devices. The strategy has been evaluated through the design of an ultra low voltage Xor based adder at supply voltages varying from 140–160 mV and temperature range 27–50 °C at 1 kHz frequency. The adder under optimal body bias consumes 4.67 percent less energy than zero body bias at Vdd=150mV and frequency of 1 kHz. The adder is fully functional for one thousand Monte Carlo simulations at optimal back bias voltage. The yield has improved by 0.4 percent in optimal back bias voltage compared to zero body bias. The results show the lowest Energy per cycle, variability and high functional yield for the obtained optimal body bias voltage. Also, additional analysis confirms the dependency of optimal body bias voltage on the switching activity and operating conditions for a given technology. We also show that the relative energy variability is larger than the delay variability over the back bias voltage range.

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