论文信息 - Noise-tolerant dynamic circuit design

Noise-tolerant dynamic circuit design

Noise in deep submicron technology combined with the move towards dynamic circuit techniques for higher performance have raised concerns about reliability and energy efficiency of VLSI systems in the deep submicron era. To address this problem, a new noise-tolerant dynamic circuit technique is presented. In addition, the average noise threshold energy (ANTE) and the energy normalized ANTE metrics are proposed for quantifying the noise immunity and energy efficiency, respectively, of circuit techniques. Simulation results in 0.35 micron CMOS for NAND gate designs indicate that the proposed technique improves the ANTE and energy normalized ANTE by 2.54X and 2.25X over the conventional domino circuit. The improvement in energy normalized ANTE is 1.22X higher than the existing noise-tolerance techniques. A full adder design based on the proposed technique improves the ANTE and energy normalized ANTE by 3.7X and 1.95X over the conventional dynamic circuit. In comparison, the static circuit improves ANTE by 2.2X but degrades the energy normalized ANTE by 11%. In addition, the proposed technique has a smaller area overhead (69%) as compared to the static circuit whose area overhead is 98%.

Naresh R. Shanbhag | Lei Wang | Naresh R Shanbhag | Lei Wang

[1] Christer Svensson,et al. Noise in digital dynamic CMOS circuits , 1994 .

[2] E. T. Lewis. An analysis of interconnect line capacitance and coupling for VLSI circuits , 1984 .

[3] Jan M. Rabaey,et al. Digital Integrated Circuits: A Design Perspective , 1995 .

[4] Anirudh Devgan. Efficient coupled noise estimation for on-chip interconnects , 1997, ICCAD 1997.

[5] David D. Ling,et al. Power Supply Noise Analysis Methodology For Deep-submicron Vlsi Chip Design , 1997, Proceedings of the 34th Design Automation Conference.

[6] G.A. Katopis,et al. Delta-I noise specification for a high-performance computing machine , 1985, Proceedings of the IEEE.

[7] K. L. Shepard,et al. Noise in deep submicron digital design , 1996, ICCAD 1996.

[8] Anirudh Devgan,et al. Efficient coupled noise estimation for on-chip interconnects , 1997, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[9] Soha Hassoun,et al. A 200-MHz 64-bit Dual-Issue CMOS Microprocessor , 1992, Digit. Tech. J..

[10] Yukihito Oowaki,et al. Noise suppression scheme for gigabit-scale and gigabyte/s data-rate LSI's , 1998 .

[11] Naresh R. Shanbhag,et al. A Mathematical Basis For Power-Reduction In Digital VLSI Systems , 1997 .