Modeling 20-nm Germanium FinFET With the Industry Standard FinFET Model
暂无分享,去创建一个
Chenming Hu | Yogesh Singh Chauhan | Sourabh Khandelwal | Juan Pablo Duarte | C. Hu | Y. Chauhan | S. Khandelwal | J. Duarte
[1] B. Duriez,et al. Scaled p-channel Ge FinFET with optimized gate stack and record performance integrated on 300mm Si wafers , 2013, 2013 IEEE International Electron Devices Meeting.
[2] G. Dewey,et al. Non-planar, multi-gate InGaAs quantum well field effect transistors with high-K gate dielectric and ultra-scaled gate-to-drain/gate-to-source separation for low power logic applications , 2010, 2010 International Electron Devices Meeting.
[3] T. Lee,et al. Demonstration of scaled Ge p-channel FinFETs integrated on Si , 2012, 2012 International Electron Devices Meeting.
[4] Sang-Pil Sim,et al. Physical understanding of low-field carrier mobility in silicon MOSFET inversion layer , 1991 .
[5] G. Groeseneken,et al. Impact of High-Mobility Materials on the Performance of Near- and Sub-Threshold CMOS Logic Circuits , 2013, IEEE Transactions on Electron Devices.
[6] C. Hsieh,et al. Germanium p-Channel FinFET Fabricated by Aspect Ratio Trapping , 2014, IEEE Transactions on Electron Devices.
[7] Ali M. Niknejad,et al. Global parameter extraction for a multi-gate MOSFETs compact model , 2010, 2010 International Conference on Microelectronic Test Structures (ICMTS).
[8] Rui Zhang,et al. High-Mobility Ge p- and n-MOSFETs With 0.7-nm EOT Using $\hbox{HfO}_{2}/\hbox{Al}_{2}\hbox{O}_{3}/\hbox{GeO}_{x}/\hbox{Ge}$ Gate Stacks Fabricated by Plasma Postoxidation , 2013, IEEE Transactions on Electron Devices.
[9] C. Hu,et al. MOSFET carrier mobility model based on gate oxide thickness, threshold and gate voltages , 1996 .