Routable technology mapping for LUT FPGAs

A routing-driven technology mapper for lookup-table, (LUT)-based field-programmable gate arrays (FPGAs) is presented. The approach is based on performing mapping aimed at routing feasibility. For an FPGA of given size (number of LUTs), the logic being implemented is distributed in such a manner that the total wire length is minimized and the routing resources are not overutilized. Simulated annealing is used to perform mapping, placement, and global routing in tandem. The algorithm can handle both combinational and sequential logic circuits, and has been implemented for combinational circuits. Experiments on MCNC benchmark circuits show encouraging results.<<ETX>>

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