Integrated circuit testing for quality assurance in manufacturing: history, current status, and future trends

Integrated circuit (IC) testing for quality assurance is approaching 50% of the manufacturing costs for some complex mixed-signal ICs. For many years the market growth and technology advancements in digital ICs were driving the developments in testing. The increasing trend to integrate information acquisition and digital processing on the same chip has spawned increasing attention to the test needs of mixed-signal ICs. The recent advances in wireless communications indicate a trend toward the integration of the RF and baseband mixed signal technologies. In this paper we examine the developments in IC testing from the historic, current status and future view points. In separate sections we address the testing developments for digital, mixed signal and RF ICs. With these reviews as context, we relate new test paradigms that have the potential to fundamentally alter the methods used to test mixed-signal and RF parts.

[1]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[2]  Yashwant K. Malaiya,et al.  A New Fault Model and Testing Technique for CMOS Devices , 1982, International Test Conference.

[3]  Phil Nigh,et al.  ASIC test cost/strategy trade-offs , 1994, Proceedings., International Test Conference.

[4]  Srinivas Devadas,et al.  Test generation and verification for highly sequential circuits , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Matthew Mahoney,et al.  DSP-Based Testing of Analog and Mixed-Signal Circuits , 1987 .

[6]  Wojciech Maly,et al.  Inductive contamination analysis (ICA) with SRAM application , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[7]  John Paul Shen,et al.  The Design of Easily Testable VLSI Array Multipliers , 1984, IEEE Transactions on Computers.

[8]  Robert G. Hillman,et al.  Microelectronic Device Electrical Test Implementation Problems on Automated Test Equipment , 1982, ITC.

[9]  Younggap You,et al.  A Self-Testing Dynamic RAM Chip , 1985, IEEE Journal of Solid-State Circuits.

[10]  C. Barsotti,et al.  Very high density probing , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[11]  Vishwani D. Agrawal,et al.  Logic systems for path delay test generation , 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.

[12]  Bapiraju Vinnakota.  Monitoring power dissipation for fault detection , 1996, Proceedings of 14th VLSI Test Symposium.

[13]  Neil Weste,et al.  Principles of CMOS VLSI Design , 1985 .

[14]  Douglas B. Armstrong,et al.  On Finding a Nearly Minimal Set of Fault Detection Tests for Combinational Logic Nets , 1966, IEEE Trans. Electron. Comput..

[15]  James B. Angell,et al.  Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic , 1973, IEEE Transactions on Computers.

[16]  J. M. Soden,et al.  I/sub DDQ/ testing and defect classes-a tutorial , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

[17]  Kurt Keutzer,et al.  Delay-fault test generation and synthesis for testability under a standard scan design methodology , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Gordon W. Roberts,et al.  Arbitrary-precision signal generation for bandlimited mixed-signal testing , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[19]  John P. Hayes,et al.  Designing for high-level test generation , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Jacob A. Abraham,et al.  Characterization and Testing of Physical Failures in MOS Logic Circuits , 1984, IEEE Design & Test of Computers.

[21]  Niraj K. Jha,et al.  Detection of multiple input bridging and stuck-on faults in CMOS logic circuits using current monitoring , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[22]  Yervant Zorian,et al.  Do you practice safe test? What we found out about your habits , 1994, Proceedings., International Test Conference.

[23]  Stephen Y. H. Su,et al.  Fault Diagnosis of MOS Combinational Networks , 1982, IEEE Transactions on Computers.

[24]  Jacob A. Abraham,et al.  A novel test generation approach for parametric faults in linear analog circuits , 1996, Proceedings of 14th VLSI Test Symposium.

[25]  Donald R. Haring,et al.  Multi-threshold threshold elements , 1966, IEEE Trans. Electron. Comput..

[26]  Robert K. Brayton,et al.  Timing analysis and delay-fault test generation using path-recursive functions , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[27]  William J. Bowhers.  Filtering Methods for Fast Ultra-Low Distortion Measurements , 1982, ITC.

[28]  Thomas W. Williams,et al.  A logic design structure for LSI testability , 1977, DAC '77.

[29]  Carl Sechen,et al.  An efficient method for generating exhaustive test sets , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[30]  Tim Higgins.  Digital Signal Processing for Production Testing of Analog LSI Devices , 1982, ITC.

[31]  Scott F. Midkiff,et al.  Test generation for IDDQ testing of bridging faults in CMOS circuits , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[32]  Luke S. L. Hsieh,et al.  THD and SNR tests using the simplified Volterra series with adaptive algorithms , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[33]  V. S. Iyengar.  Delay test generation , 1988 .

[34]  Sudhakar M. Reddy,et al.  On Unified Delay Fault Testing , 1993, The Sixth International Conference on VLSI Design.

[35]  Srinivas Devadas,et al.  Test generation for highly sequential circuits , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[36]  Hideo Fujiwara,et al.  On the Acceleration of Test Generation Algorithms , 1983, IEEE Transactions on Computers.

[37]  John P. Hayes,et al.  Design of a fast, easily testable ALU , 1996, Proceedings of 14th VLSI Test Symposium.

[38]  Jacob A. Abraham,et al.  Functional Testing of Microprocessors , 1984, IEEE Transactions on Computers.

[39]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[40]  Edward J. McCluskey,et al.  An experimental chip to evaluate test techniques experiment results , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[41]  John J. Shedletsky,et al.  An Experimental Delay Test Generator for LSI Logic , 1980, IEEE Transactions on Computers.

[42]  Prathima Agrawal,et al.  Generating tests for delay faults in nonscan circuits , 1993, IEEE Design & Test of Computers.

[43]  Manoj Sachdev,et al.  Industrial relevance of analog IFA: a fact or a fiction , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[44]  Vishwani D. Agrawal,et al.  A New Method for Generating Tests for Delay Faults in Non-Scan Circuits , 1992, The Fifth International Conference on VLSI Design.

[45]  H. Ando,et al.  Testing VLSI with Random Access Scan , 1980 .

[46]  Shyang-Tai Su,et al.  Transient power supply current testing of digital CMOS circuits , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[47]  Toshihiro Arima,et al.  Test generation systems in Japan , 1975, DAC '75.

[48]  Robert M. Gray,et al.  Oversampled Sigma-Delta Modulation , 1987, IEEE Trans. Commun..

[49]  J. Patel,et al.  Testing in two-dimensional iterative logic arrays , 1987 .

[50]  Niraj K. Jha.  Multiple Stuck-Open Fault Detection in CMOS Logic Circuits , 1988, IEEE Trans. Computers.

[51]  John Paul Shen,et al.  Extraction and simulation of realistic CMOS faults using inductive fault analysis , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[52]  Kozo Kinoshita,et al.  Row/column pattern sensitive fault detection in RAMs via built-in self-test , 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[53]  Rodham E. Tulloss,et al.  The Test Access Port and Boundary Scan Architecture , 1990 .

[54]  Prathima Agrawal,et al.  Test Generation for Path Delay Faults Using Binary Decision Diagrams , 1995, IEEE Trans. Computers.

[55]  M. M. Pradhan,et al.  Circular BIST with partial scan , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[56]  Barry K. Rosen,et al.  Delay test generation. I. Concepts and coverage metrics , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[57]  J. Paul Roth,et al.  Diagnosis of automata failures: a calculus and a method , 1966 .

[58]  Gordon W. Roberts,et al.  A built-in self-test strategy for wireless communication systems , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[59]  John Paul Shen,et al.  Inductive Fault Analysis of MOS Integrated Circuits , 1985, IEEE Design & Test of Computers.

[60]  Yervant Zorian,et al.  An effective BIST scheme for ring-address type FIFOs , 1994, Proceedings., International Test Conference.

[61]  Eric Rosenfeld,et al.  DSP CALIBRATION FOR ACCURATE TIME WAVEFORM RECONSTRUCTION , 1991, 1991, Proceedings. International Test Conference.

[62]  Koji Karube,et al.  ADVANCED MIXED SIGNAL TESTING BY DSP LOCALIZED TESTER , 1991, 1991, Proceedings. International Test Conference.

[63]  Edward J. McCluskey.  Verification Testing - A Pseudoexhaustive Test Technique , 1984, IEEE Trans. Computers.

[64]  Franc Brglez.  Digital Signal Processing Considerations in Filter-Codec Testing , 1981, ITC.

[65]  Kamran Eshraghian,et al.  Principles of CMOS VLSI Design: A Systems Perspective , 1985 .

[66]  Farid Matta,et al.  THE FUTURE FOR HIGH PERFORMANCE WAFER TEST) , 1988 .

[67]  G. A. Perone,et al.  A Closer Look at Testing Costs , 1982, ITC.

[68]  Karl F. Zimmermann.  SiProbe-a new technology for wafer probing , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[69]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[70]  Leslie Ackner,et al.  Frequency enhancement of digital VLSI test systems , 1990, Proceedings. International Test Conference 1990.

[71]  John P. Hayes,et al.  Pseudo-Boolean Logic Circuits , 1986, IEEE Transactions on Computers.

[72]  Robert A. Witte.  Spectrum and network measurements , 1991 .

[73]  John Paul Shen,et al.  Systematic Characterization of Physical Defects for Fault Analysis of MOS IC Cells , 1984, ITC.

[74]  K. Loftstrom.  A demonstration IC for the P1149.4 mixed signal test standard , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[75]  Kenneth R. Laker,et al.  Design of analog integrated circuits and systems , 1994 .

[76]  Vishwani D. Agrawal,et al.  High-performance circuit testing with slow-speed testers , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[77]  Michael H. Schulz,et al.  SOCRATES: a highly efficient automatic test pattern generation system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[78]  Frans P. M. Beenker,et al.  A realistic fault model and test algorithms for static random access memories , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[79]  R. L. Wadsack,et al.  Fault modeling and logic simulation of CMOS and MOS integrated circuits , 1978, The Bell System Technical Journal.

[80]  Steve Barton,et al.  Characterization of high-speed (above 500 MHz) devices using advanced ATE-techniques, results and device problems , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[81]  Michael H. Schulz,et al.  DYNAMITE: an efficient automatic test pattern generation system for path delay faults , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[82]  Yervant Zorian,et al.  Built-in self-test for digital integrated circuits , 1994, AT&T Technical Journal.

[83]  Robert C. Aitken,et al.  IDDQ testing as a component of a test suite: The need for several fault coverage metrics , 1992, J. Electron. Test..

[84]  Stephen K. Sunter,et al.  The P1149.4 Mixed Signal Test Bus: costs and benefits , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).

[85]  Arthur D. Friedman,et al.  Easily Testable Iterative Systems , 1973, IEEE Transactions on Computers.

[86]  John J. Durgavich,et al.  Considerations for, and Impact of, the ATE/UUT Interface , 1978, IEEE Transactions on Instrumentation and Measurement.

[87]  Kenneth M. Butler,et al.  Assessing fault model and test quality , 1991 .

[88]  John P. Hayes,et al.  A hierarchical test generation methodology for digital circuits , 1990, J. Electron. Test..

[89]  D. C. King.  Diagnosis and reliable design of digital systems , 1977 .

[90]  Janak H. Patel,et al.  Design and Algorithms for Parallel Testing of Random Access and Content Addressable Memories , 1987, 24th ACM/IEEE Design Automation Conference.

[91]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .

[92]  Scott F. Midkiff,et al.  ON TEST GENERATION FOR I/sub DDQ/ TESTING OF BRIDGING FAULTS IN CMOS CIRCUITS , 1991, 1991, Proceedings. International Test Conference.

[93]  John P. Hayes,et al.  A Functional Approach to Testing Bit-Sliced Microprocessors , 1981, IEEE Transactions on Computers.