Methodologies and algorithms for testing switch-based NoC interconnects
暂无分享,去创建一个
[1] Luigi Carro,et al. Power-aware noc reuse on the testing of core-based systems , 2003, International Test Conference, 2003. Proceedings. ITC 2003..
[2] Dhabaleswar K. Panda,et al. Implementing Multidestination Worms in Switch-Based Parallel Systems: Architectural Alternatives and Their Impact , 2000, IEEE Trans. Parallel Distributed Syst..
[3] Partha Pratim Pande,et al. Design of a switch for network on chip applications , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..
[4] Erik Jan Marinissen,et al. A structured and scalable mechanism for test access to embedded reusable cores , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[5] Alain Greiner,et al. A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.
[6] Pierre G. Paulin,et al. System-on-chip beyond the nanometer wall , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[7] André Ivanov,et al. Indirect test architecture for SoC testing , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[8] Yervant Zorian,et al. Testing Embedded-Core-Based System Chips , 1999, Computer.
[9] Kees G. W. Goossens,et al. Bringing communication networks on a chip: test and verification implications , 2003, IEEE Commun. Mag..
[10] Sudhakar Yalamanchili,et al. Interconnection Networks: An Engineering Approach , 2002 .
[11] Partha Pratim Pande,et al. Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs , 2004, GLSVLSI '04.
[12] Luca Benini,et al. Networks on Chips : A New SoC Paradigm , 2022 .
[13] Partha Pratim Pande,et al. Timing analysis of network on chip architectures for MP-SoC platforms , 2005, Microelectron. J..
[14] Partha Pratim Pande,et al. Switch-based interconnect architecture for future systems on chip , 2003, SPIE Microtechnologies.
[15] Radu Marculescu,et al. On-chip traffic modeling and synthesis for MPEG-2 video applications , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[16] W. Dally,et al. Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[17] L. Benini,et al. Xpipes: a network-on-chip architecture for gigascale systems-on-chip , 2004, IEEE Circuits and Systems Magazine.
[18] Yervant Zorian,et al. Functional test for shifting-type FIFOs , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.
[19] Baosheng Wang,et al. Designs for reducing test time of distributed small embedded SRAMs , 2004 .
[20] Axel Jantsch,et al. A network on chip architecture and design methodology , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.