A beta model for estimating the testability and coverage distributions of a VLSI circuit
暂无分享,去创建一个
[1] Sunil Jain,et al. Statistical Fault Analysis , 1985, IEEE Design & Test of Computers.
[2] Vishwani D. Agrawal,et al. Test generation by fault sampling , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.
[3] Joel C. Kleinman,et al. Proportions with Extraneous Variance: Single and Independent Samples , 1973 .
[4] David Bryan,et al. Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.
[5] Williams Da,et al. The analysis of binary responses from toxicological experiments involving reproduction and teratogenicity. , 1975 .
[6] Oscar H. Ibarra,et al. Polynomially Complete Fault Detection Problems , 1975, IEEE Transactions on Computers.
[7] Peter J. Danaher. A Markov mixture model for magazine exposure , 1989 .
[8] Douglas B. Armstrong,et al. A Deductive Method for Simulating Faults in Logic Circuits , 1972, IEEE Transactions on Computers.
[9] S. From,et al. Confidence intervals for expected coverage from a beta testability model , 1992 .
[10] Prabhakar Goel,et al. An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.
[11] Vishwani D. Agrawal,et al. A Statistical Theory of Digital Circuit Testability , 1990, IEEE Trans. Computers.
[12] D. M. Smith. Algorithm AS 189: Maximum Likelihood Estimation of the Parameters of the Beta Binomial Distribution , 1983 .