A Low Error, Hardware Efficient Logarithmic Multiplier
暂无分享,去创建一个
Bhaskara Rao Jammu | Sreehari Veeramachaneni | L. Guna Sekhar Sai Harsha | Nalini Bodasingi | S. NoorMohammad | S. Veeramachaneni | Nalini Bodasingi | B. Jammu | L. G. S. S. Harsha | S. NoorMohammad
[1] Bruce F. Cockburn,et al. An Improved Logarithmic Multiplier for Energy-Efficient Neural Computing , 2021, IEEE Transactions on Computers.
[2] Sri Parameswaran,et al. Minimally Biased Multipliers for Approximate Integer and Floating-Point Multiplication , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[3] Vassilis Paliouras,et al. Logarithmic Number System for Low-Power Arithmetic , 2000, PATMOS.
[4] Luis Ceze,et al. Architecture support for disciplined approximate programming , 2012, ASPLOS XVII.
[5] Fred J. Taylor,et al. A 20 Bit Logarithmic Number System Processor , 1988, IEEE Trans. Computers.
[6] Earl E. Swartzlander,et al. Sign/Logarithm Arithmetic for FFT Implementation , 1983, IEEE Transactions on Computers.
[7] Kaushik Roy,et al. Analysis and characterization of inherent application resilience for approximate computing , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).
[8] John N. Mitchell,et al. Computer Multiplication and Division Using Binary Logarithms , 1962, IRE Trans. Electron. Comput..
[9] David M. Lewis. Interleaved Memory Function Interpolators with Application to an Accurate LNS Arithmetic Unit , 1994, IEEE Trans. Computers.
[10] M. Combet,et al. Computation of the Base Two Logarithm of Binary Numbers , 1965, IEEE Trans. Electron. Comput..
[11] Thomas A. Brubaker,et al. Multiplication Using Logarithms Implemented with Read-Only Memory , 1975, IEEE Transactions on Computers.
[12] Fabrizio Lombardi,et al. Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications , 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.
[13] Roberto Muscedere,et al. Efficient techniques for binary-to-multidigit multidimensional logarithmic number system conversion using range-addressable look-up tables , 2005, IEEE Transactions on Computers.
[14] Vassilis Paliouras,et al. Low-Power Logarithmic Number System Addition/Subtraction and Their Impact on Digital Filters , 2013, IEEE Trans. Computers.
[15] ERNEST L. HALL,et al. Generation of Products and Quotients Using Approximate Binary Logarithms for Digital Filtering Applications , 1970, IEEE Transactions on Computers.
[16] David Lewis,et al. A 30-b integrated logarithmic number system processor , 1991 .
[17] Earl E. Swartzlander,et al. The Sign/Logarithm Number System , 1975, IEEE Transactions on Computers.
[18] Demetrios K. Kostopoulos,et al. An Algorithm for the Computation of Binary Logarithms , 1991, IEEE Trans. Computers.
[19] N. Kingsbury,et al. Digital filtering using logarithmic arithmetic , 1971 .
[20] Reinhard Männer. A Fast Integer Binary Logarithm of Large Arguments , 1987, IEEE Micro.
[21] Khalid H. Abed,et al. CMOS VLSI Implementation of a Low-Power Logarithmic Converter , 2003, IEEE Trans. Computers.
[22] Ching-Farn Eric Wu,et al. A Hybrid Number System Processor with Geometric and Complex Arithmetic Capabilities , 1991, IEEE Trans. Computers.
[23] Durgesh Nandan,et al. An efficient VLSI architecture design for logarithmic multiplication by using the improved operand decomposition , 2017, Integr..
[24] Khalid H. Abed,et al. VLSI Implementation of a Low-Power Antilogarithmic Converter , 2003, IEEE Trans. Computers.