Syndrome simulation and syndrome test for unscanned interconnects
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[1] Chauchin Su,et al. A universal BIST methodology for interconnects , 1993, 1993 IEEE International Symposium on Circuits and Systems.
[2] John P. Hayes,et al. CHECK SUM METHODS FOR TEST DATA COMPRESSION. , 1976 .
[3] Marcelo Lubaszewski,et al. On the design of self-checking boundary scannable boards , 1992, Proceedings International Test Conference 1992.
[4] John P. Hayes,et al. Transition Count Testing of Combinational Logic Circuits , 1976, IEEE Transactions on Computers.
[5] Jacob Savir,et al. Syndrome-Testable Design of Combinational Circuits , 1980, IEEE Transactions on Computers.
[6] Wu-Tung Cheng,et al. Diagnosis for wiring interconnects , 1990, Proceedings. International Test Conference 1990.
[7] Vinod K. Agarwal,et al. Testing and diagnosis of interconnects using boundary scan architecture , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.
[8] Chauchin Su. Random testing of interconnects in a boundary scan environment , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.
[9] George Markowsky,et al. The Weighted Syndrome Sums Approach to VLSI Testing , 1981, IEEE Transactions on Computers.
[10] George Markowsky,et al. Syndrome-Testability Can be Achieved by Circuit Modification , 1981, IEEE Transactions on Computers.
[11] Shyh-Jye Jou,et al. An I/sub DDQ/ based built-in concurrent test technique for interconnects in a boundary scan environment , 1994, Proceedings., International Test Conference.
[12] Gordon R. McLeod. Built-in system test and fault location , 1994, Proceedings., International Test Conference.