CMOS ASIC devices for the measurement of short time intervals

Two time-to-digital converters are designed, with special emphasis on searching for and modeling the causes of timing jitter in CMOS devices. The time base is formed by an external high-frequency three-phase clock in the first design and by tapped on-chip delay-lines in the second circuit. The single-shot resolutions of the circuits are about 7 and 0.5 ns.<<ETX>>