A fault-tolerant computing system for digital signal processing

Major advancements have been made in the areas of fault-tolerant computing, parallel and distributed computing, and digital signal processing (DSP) microprocessors. While each discipline continues to grow and develop, little has been done to combine their features. By doing so, a number of problems can be resolved. This dissertation addresses two such important problems. The first is the need for DSP systems with higher levels of both performance and fault tolerance. The second is the need for methods to design and develop new multiprocessor and distributed systems in a way that reduces the escalating costs of this extremely complex task. In addressing these two problems, three objectives are identified. The first is the creation of a new system for DSP which provides higher levels of performance and fault tolerance over traditional single-processor or non-redundant DSP designs. This objective is achieved by first considering the requirements of DSP applications, and then correlating them with fault tolerance and performance issues to produce the design for a new system. The second objective is the implementation of a new system prototype without the prohibitive costs normally associated with such designs. This objective is achieved by employing state-of-the-art simulation techniques to build a system prototype completely in software. Finally, the third objective is to evaluate this new system with respect to both performance and fault tolerance. This final objective is achieved by using the system prototype, along with DSP applications such as digital filtering and fast Fourier transformations, to study and evaluate this new system.