A semi-folded instruction format for VLIW architecture

The cache structures in the existing VLIW systems are largely classified into the unpacked cache and the full packed cache. The degree of memory utilization in the unpacked cache is very low because instructions are loaded in the form of the unfolded instruction. On the contrary, the full packed cache loads instructions in the form of the folded instruction in order to enhance the degree of memory utilization. But the fetch time gets longer because the lengths of instructions are different. This paper proposes a new instruction format and a cache structure to eliminate NOPs. The experimental results show that the best performance can be achieved in the memory system composed of the partial packed cache as the first level cache and the full packed cache as the second level cache.