Hierarchical opto-electrical on-chip network for future multiprocessor architectures

Importance of power dissipation in NoCs, along with power reduction capability of on-chip optical interconnects, offers optical network-on-chip as a new technology solution for on-chip interconnects. In this paper, we extract analytical models for data transmission delay, power consumption, and energy dissipation of optical and traditional NoCs. Utilizing extracted models, we compare optical NoC with electrical one and calculate lower bound limit on the optical link length below which optical on-chip network loses its efficiency. Based on this constraint, we propose a novel hierarchical on-chip network architecture, named as H^2NoC, which benefits from optical transmissions in large scale SoCs and overcomes the scalability problem resulted from lower bound limit on the optical link length. Performing a series of simulation-based experiments, we study efficiency of H^2NoC along with its power and energy consumption and data transmission delay. Furthermore, the impact of network size, traffic pattern, and packet size distribution on the prominence of the proposed architecture over traditional NoC and non-hierarchical ONoC is addressed in this paper. Our experimental results verify that the proposed hierarchical architecture outperforms non-hierarchical ONoC for moderate and large scale MPSoCs, while its prominence degrades for small number of processing cores.

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