Hierarchical Fault Response Modeling of Analog/RF Circuits by Gurusubrahmaniyan Subrahmaniyan Radhakrishnan A Thesis Presented in Partial Fulfillment of the Requirements for the Degree Master of Science Approved November 2010 by the Graduate Supervisory Committee: Sule Ozev, Chair

i ABSTRACT In this thesis two methodologies have been proposed for evaluating the fault response of analog/RF circuits. These proposed approaches are used to evaluate the response of the faulty circuit in terms of specifications/measurements. Faulty response can be used to evaluate important test metrics like fail probability, fault coverage and yield coverage of given measurements under process variations. Once the models for faulty and fault free circuit are generated, one needs to perform Monte Carlo sampling (as opposed to Monte Carlo simulations) to compute these statistical parameters with high accuracy. The first method is based on adaptively determining the order of the model based on the error budget in terms of computing the statistical metrics and position of the threshold(s) to decide how precisely necessary models need to be extracted. In the second method, using hierarchy in process variations a hybrid of heuristics and localized linear models have been proposed. Experiments on LNA and Mixer using the adaptive model order selection procedure can reduce the number of necessary simulations by 7.54x and 7.03x respectively in the computation of fail probability for an error budget of 2%. Experiments on LNA using the hybrid approach can reduce the number of necessary simulations by 21.9x and 17x for four and six output parameters cases for improved accuracy in test statistics estimation. ii ACKNOWLEDGMENTS Although this thesis book lists only one author, in reality the ideas it molds together were contributed and refined by many extraordinarily insightful colleagues. My first thanks go to the almighty for directing me to Prof. Sule Ozev to conduct this masters research. On most days I leave her office after the meeting wondering if I have really got the benefit of my 18 years of science education. My interactions with her have proved time and again that learning is a continuous process and this gives me great deal of enthusiasm to delve deep into new and obscure topics. I thank her for all the guidance during this enduring period of research. I would also like to thank Christen for promptly agreeing to serve on the defense committee. I am indebted to my parents who have for all the motivation, emotional and financial support much needed during my educational career. I am thankful to Ender Yilmaz, Afsaneh Nassery, Osman Erol and other members of Prof. Ozev's research group for all the fruitful discussions not only restricted to research, but …

[1]  Salvador Mir,et al.  Evaluation of Analog/RF Test Measurements at the Design Stage , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Sule Ozev,et al.  Dynamic test scheduling for analog circuits for improved test quality , 2008, 2008 IEEE International Conference on Computer Design.

[3]  M. Hubert,et al.  High-Breakdown Robust Multivariate Methods , 2008, 0808.0657.

[4]  Fang Liu,et al.  Efficient simulation of parametric faults for multi-stage analog circuits , 2007, 2007 IEEE International Test Conference.

[5]  Fang Liu,et al.  Test yield estimation for analog/RF circuits over multiple correlated measurements , 2007, 2007 IEEE International Test Conference.

[6]  Fang Liu,et al.  Statistical Test Development for Analog Circuits Under High Process Variations , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Yiorgos Makris,et al.  Non-RF to RF Test Correlation Using Learning Machines: A Case Study , 2007, 25th IEEE VLSI Test Symposium (VTS'07).

[8]  José L. Ausín,et al.  A 1-MHz Area-Efficient On-Chip Spectrum Analyzer for Analog Testing , 2006, J. Electron. Test..

[9]  Abhijit Chatterjee,et al.  Alternate Test of RF Front Ends with IP Constraints: Frequency Domain Test Generation and Validation , 2006, 2006 IEEE International Test Conference.

[10]  Guoyong Shi,et al.  Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Guido Gronthoud,et al.  Functional vs. multi-VDD testing of RF circuits , 2005, IEEE International Conference on Test, 2005..

[12]  Keith A. Jenkins,et al.  On-chip spectrum analyzer for analog built-in self test , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[13]  Fang Liu,et al.  Hierarchical analysis of process variation for mixed-signal systems , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[14]  Xin Li,et al.  Robust analog/RF circuit design with projection-based posynomial modeling , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[15]  D. Blaauw,et al.  Statistical timing analysis for intra-die process variations with spatial correlations , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

[16]  Abhijit Chatterjee,et al.  Concurrent transient fault simulation for analog circuits , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Hans G. Kerkhoff,et al.  Fast fault simulation for nonlinear analog circuits , 2003, IEEE Design & Test of Computers.

[18]  M. W. Tian,et al.  Worst case tolerance analysis of linear analog circuits using sensitivity bands , 2000 .

[19]  Stephen K. Sunter,et al.  Test metrics for analog parametric faults , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[20]  L. S. Milor,et al.  A tutorial introduction to research on analog and mixed-signal circuit testing , 1998 .

[21]  C. Shi,et al.  Rapid Frequency-domain Analog Fault Simulation Under Parameter Tolerances , 1997, Proceedings of the 34th Design Automation Conference.

[22]  Saad T. Bakir,et al.  Tolerance Design: A Handbook for Developing Optimal Specifications , 1996 .

[23]  Abhijit Chatterjee,et al.  Fault-based automatic test generator for linear analog circuits , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[24]  Bozena Kaminska,et al.  Analog circuit testing based on sensitivity computation and new circuit modeling , 1993, Proceedings of IEEE International Test Conference - (ITC).

[25]  Brown,et al.  Defect Level as a Function of Fault Coverage , 1981, IEEE Transactions on Computers.

[26]  Genichi Taguchi,et al.  Performance analysis design , 1978 .

[27]  David H. Evans.  An Application of Numerical Integration Techniclues to Statistical Toleraucing , 1967 .

[28]  PETER J. ROUSSEEUW,et al.  Computing LTS Regression for Large Data Sets , 2005, Data Mining and Knowledge Discovery.

[29]  Bozena Kaminska,et al.  Analog circuit fault diagnosis based on sensitivity computation and functional testing , 1992, IEEE Design & Test of Computers.