论文信息 - Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits

Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched Circuits

Standby-power dissipation in ultra-deep submicron CMOS can be reduced by power switching. As the cut-off device has a strong impact on area consumption, minimum power-down time, signal delay and leakage suppression, a proper sizing of this device is of general importance. Therefore a two level compact simulation methodology is proposed which provides fast and accurate CAD support to the switch design task.

Stephan Henzler | Doris Schmitt-Landsiedel | Georg Georgakos | Jörg Berthold

[1] Stephan Henzler,et al. Fast power-efficient circuit-block switch-off scheme , 2004 .

[2] Stephan Henzler,et al. Design Aspects and Technological Scaling Limits of ZigZag Circuit Block Switch-Off Schemes , 2003, VLSI-SOC.

[3] Shin'ichiro Mutoh,et al. 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS , 1995, IEEE J. Solid State Circuits.

[4] P. R. van der Meer,et al. New standby–current reduction technique for deep sub–micron VLSI CMOS circuits: Smart series switch , 2002 .

[5] R.V. Joshi,et al. New digital circuit techniques for total standby leakage reduction in nano-scale SOI technology , 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

[6] H. Kawaguchi,et al. Zigzag super cut-off CMOS (ZSCCMOS) block activation with self-adaptive voltage level controller: an alternative to clock-gating scheme in leakage dominant era , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[7] T. Sakurai,et al. A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current , 2000, IEEE Journal of Solid-State Circuits.

[8] A. R. Newton,et al. Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .

[9] Anantha Chandrakasan,et al. Transistor sizing issues and tool for multi-threshold CMOS technology , 1997, DAC.