Design and implementation of high-speed JPEG image encoding system based on FPGA

This paper presents a design scheme of high-speed JPEG image encoding system based on FPGA. The encoder of this system can achieve the parallel processing of the input image sequences and work in pipeline mode. According to simulation test and FPGA verification, the whole system, which meets the JPEG standard for the requirements of image compression quality and compression ratio, can support the processing speed of 400fps for 1024×768 gray images, when the encoder core number is 4 and the working frequency is 100MHz. The high performance of the system can fully satisfy the demands of high-speed and real time encoding applications.