Assessment of 28 nm UTBB FD-SOI technology platform for RF applications: Figures of merit and effect of parasitic elements

Abstract This work provides a detailed study of 28 nm fully-depleted silicon-on-insulator (FD-SOI) planar ultra-thin body and BOX (UTBB) MOSFETs for high frequency applications. All parasitic elements such as the parasitic gate and source/drain series resistances, total capacitances are extracted and their effects on RF performance are analyzed and compared with previous work on similar devices. Two main RF figures of merit (FoM) such as the current gain cut-off frequency ( f T ) and the maximum oscillation frequency ( f max ) are determined. It is shown that f T of ∼280 GHz and f max of ∼250 GHz are achievable in the shortest devices. Based on the extracted parameters, the validation of the small-signal equivalent circuit used for modeling UTBB MOSFETs is investigated by comparing simulated and measured S -parameters.

[1]  Stefaan Decoutere,et al.  MOSFET bias dependent series resistance extraction from RF measurements , 2003 .

[2]  A. Gharsallah,et al.  Ultrawide Frequency Range Crosstalk Into Standard and Trap-Rich High Resistivity Silicon Substrates , 2011, IEEE Transactions on Electron Devices.

[3]  K. Ohuchi,et al.  Impact of BOX scaling on 30 nm gate length FD SOI MOSFET , 2005, 2005 IEEE International SOI Conference Proceedings.

[4]  J.-P. Raskin,et al.  High-Frequency Noise Performance of 60-nm Gate-Length FinFETs , 2008, IEEE Transactions on Electron Devices.

[5]  A. Gharsallah,et al.  RF SOI CMOS technology on commercial trap-rich high resistivity SOI wafer , 2012, 2012 IEEE International SOI Conference (SOI).

[6]  J.-P. Raskin,et al.  RF-extraction methods for MOSFET series resistances: A fair comparison , 2008, 2008 7th International Caribbean Conference on Devices, Circuits and Systems.

[7]  B. Riccò,et al.  Characterization of polysilicon-gate depletion in MOS structures , 1996, IEEE Electron Device Letters.

[8]  G. Pailloncy,et al.  High-Frequency Performance of Schottky Source/Drain Silicon pMOS Devices , 2008, IEEE Electron Device Letters.

[9]  Jean-Pierre Raskin,et al.  RF Performance of SOI CMOS Technology on Commercial 200-mm Enhanced Signal Integrity High Resistivity SOI Substrate , 2014, IEEE Transactions on Electron Devices.

[10]  이희승,et al.  Novel Method for Accurate Extraction of fMAX for Nano-Scale MOSFETs , 2004 .

[11]  Ph. Benech,et al.  State of the art 200 GHz passive components and circuits integrated in advanced thin SOI CMOS technology on High Resistivity substrate , 2006, 2006 IEEE international SOI Conferencee Proceedings.

[12]  Denis Flandre,et al.  Substrate crosstalk reduction using SOI technology , 1997 .

[13]  A. Vandooren,et al.  Mixed-signal performance of sub-100nm fully-depleted SOI devices with metal gate, high K (HfO/sub 2/) dielectric and elevated source/drain extensions , 2003, IEEE International Electron Devices Meeting 2003.

[14]  Y.C. Sun,et al.  0.13 μm Low Voltage Logic Based RF CMOS Technology with 115GHz fT and 80GHz fMAX , 2003, 2003 33rd European Microwave Conference, 2003.

[15]  N. Camilleri,et al.  Extracting small-signal model parameters of silicon MOSFET transistors , 1994, 1994 IEEE MTT-S International Microwave Symposium Digest (Cat. No.94CH3389-4).

[16]  J.-P. Raskin,et al.  Revised RF Extraction Methods for Deep Submicron MOSFETs , 2008, 2008 European Microwave Integrated Circuit Conference.

[17]  Sorin Cristoloveanu,et al.  Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture , 2002 .

[18]  Jean-Pierre Raskin,et al.  High-frequency performance of Schottky Barrier p-MOSFET devices , 2008 .

[19]  Wooyeol Choi,et al.  Scalable small-signal modeling of RF CMOS FET based on 3-D EM-based extraction of parasitic effects , 2009, 2009 IEEE MTT-S International Microwave Symposium Digest.

[20]  Jean-Pierre Raskin,et al.  SOI technology: An opportunity for RF designers? , 2023, Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test.

[21]  N. Fel,et al.  A New Approach for SOI Devices Small-Signal Parameters Extraction , 2000 .

[22]  W. Lee,et al.  A novel CVD-SiBCN Low-K spacer technology for high-speed applications , 2008, 2008 Symposium on VLSI Technology.

[23]  F. Danneville,et al.  What are the limiting parameters of deep-submicron MOSFETs for high frequency applications? , 2003, IEEE Electron Device Letters.

[24]  Denis Flandre,et al.  Effect of parasitic elements on UTBB FD SOI MOSFETs RF figures of merit , 2014 .

[25]  Zhengsheng Han,et al.  SOI technology for radio-frequency integrated-circuit applications , 2006 .

[26]  Kah-Wee Ang,et al.  Strained ${\rm n}$-MOSFET With Embedded Source/Drain Stressors and Strain-Transfer Structure (STS) for Enhanced Transistor Performance , 2008, IEEE Transactions on Electron Devices.

[27]  F. Danneville,et al.  RF Small-Signal Analysis of Schottky-Barrier p-MOSFET , 2008, IEEE Transactions on Electron Devices.

[28]  O. Faynot,et al.  0.25 μm fully depleted SOI MOSFETs for RF mixed analog-digital circuits, including a comparison with partially depleted devices with relation to high frequency noise parameters , 2002 .

[29]  Jean-Pierre Raskin,et al.  New RF extrinsic resistances extraction procedure for deep-submicron MOS transistors , 2010 .

[30]  M. Ostling,et al.  Control of Self-Heating in Thin Virtual Substrate Strained Si MOSFETs , 2006, IEEE Transactions on Electron Devices.

[31]  J. Raskin,et al.  Accurate SOI MOSFET characterization at microwave frequencies for device performance optimization and analog modeling , 1998 .

[32]  Denis Flandre,et al.  Influence of device engineering on the analog and RF performances of SOI MOSFETs , 2003 .

[33]  Jean-Pierre Colinge,et al.  Direct extraction method of SOI MOSFET transistors parameters , 1996, Proceedings of International Conference on Microelectronic Test Structures.

[34]  Denis Flandre,et al.  Wide frequency band assessment of 28 nm FDSOI technology platform for analogue and RF applications , 2014 .

[35]  V. Fusco,et al.  Low-loss CPW lines on surface stabilized high-resistivity silicon , 1999, IEEE Microwave and Guided Wave Letters.

[36]  D. Lederer,et al.  New substrate passivation method dedicated to HR SOI wafer fabrication with increased substrate resistivity , 2005, IEEE Electron Device Letters.

[37]  Frédéric Boeuf,et al.  Impact of strained-channel n-MOSFETs with a SiGe virtual substrate on dielectric interface quality evaluated by low frequency noise measurements , 2007, Microelectron. Reliab..

[38]  O. Rozeau,et al.  28nm FDSOI technology platform for high-speed low-voltage digital applications , 2012, 2012 Symposium on VLSI Technology (VLSIT).