Dickson charge pump circuit design with parasitic resistance in power lines

Parasitic resistance in power and ground lines is considered for Dickson charge pump circuit designs, and its equivalent model is modified for low voltage IC designs. When the optimization is done for maximized output current or for minimized rise time, it is not necessary to increase the number of stages, but it is necessary to increase the pumping capacitors. The impact of the parasitic resistance in addition to the parasitic capacitance on charge pump circuit performances is discussed. The analytical results are compared with the SPICE simulation and the model has a sufficient accuracy within a typical error of 10%.