Low-Temperature Transport Characteristics and Quantum-Confinement Effects in Gate-All-Around Si-Nanowire N-MOSFET

Gate-all-around n-MOSFETs with Si-nanowire (~7 nm) as the channel body are fabricated and characterized for their low-temperature behavior (~5 K to 295 K). I<sub>DS</sub>-V<sub>GS</sub> characteristics at low V<sub>DS</sub> (~50 mV) exhibit a decrease in current with decreasing temperature in strong inversion up to about ~200 K. However, at high V<sub>DS</sub>, drain current reverts to typical temperature behavior, i.e., I<sub>DS</sub> increases with the reducing temperature due to the increase in phonon-limited mobility (mu<sub>ph</sub>)- It is inferred that, at low V<sub>DS</sub> the enhancement in mu<sub>ph</sub> at a reduced temperature could be possibly masked by the intersubband scattering on account of subband splitting due to quantum-confinement effects as indicated by subband calculations for nanowire structures.

[1]  R. Williams,et al.  Chemical vapor deposition of Si nanowires nucleated by TiSi2 islands on Si , 2000 .

[2]  S. T. Lee,et al.  Small-Diameter Silicon Nanowire Surfaces , 2003, Science.

[3]  T. Cao,et al.  Logic Gates and Computation from Assembled Nanowire Building Blocks , 2001 .

[4]  S.C. Rustagi,et al.  High-performance fully depleted silicon nanowire (diameter /spl les/ 5 nm) gate-all-around CMOS devices , 2006, IEEE Electron Device Letters.

[5]  Kyeongjae Cho,et al.  Bandstructure modulation for carbon nanotubes in a uniform electric field , 2002 .

[6]  Charles M. Lieber,et al.  High Performance Silicon Nanowire Field Effect Transistors , 2003 .

[7]  D. Munteanu,et al.  Influence of band-structure on electron ballistic transport in silicon nanowire MOSFET's: an atomistic study , 2005, Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005..

[8]  Jeffrey Bokor,et al.  Fabrication of planar silicon nanowires on silicon-on-insulator using stress limited oxidation , 1997 .

[9]  Scanned electrical probe characterization of carrier transport behavior in InAs nanowires , 2006 .

[10]  B. Ryu,et al.  High performance 5nm radius Twin Silicon Nanowire MOSFET (TSNWFET) : fabrication on bulk si wafer, characteristics, and reliability , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[11]  Yuan Taur,et al.  Fundamentals of Modern VLSI Devices , 1998 .

[12]  Chenming Hu,et al.  5nm-gate nanowire FinFET , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[13]  C.R. Cleavelin,et al.  Quantum-mechanical effects in trigate SOI MOSFETs , 2006, IEEE Transactions on Electron Devices.

[14]  Charles M. Lieber,et al.  Diameter-controlled synthesis of single-crystal silicon nanowires , 2001 .

[15]  Gerhard Klimeck,et al.  Bandstructure and orientation effects in ballistic Si and Ge nanowire FETs , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[16]  G. Knoblinger,et al.  Low-temperature electron mobility in Trigate SOI MOSFETs , 2006, IEEE Electron Device Letters.

[17]  G. Knoblinger,et al.  Temperature effects on trigate SOI MOSFETs , 2006, IEEE Electron Device Letters.

[18]  J.A. Kenrow.  Characterization and analysis of OFET devices based on TCAD simulations , 2005, IEEE Transactions on Electron Devices.

[19]  Massimo Rudan,et al.  Quantum-mechanical analysis of the electrostatics in silicon-nanowire and carbon-nanotube FETs , 2005 .

[20]  Massimo Rudan,et al.  Investigating the performance limits of silicon-nanowire and carbon-nanotube FETs , 2005 .