Self-checking scheme for the on-line testing of power supply noise
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Cecilia Metra | Michele Favalli | Bruno Riccò | Luca Schiano | B. Riccò | C. Metra | M. Favalli | L. Schiano
[1] Jien Chung Lo,et al. Novel area-time efficient static CMOS totally self-checking comparator , 1993 .
[2] Dimitris Nikolos. Self-Testing Embedded Two-Rail Checkers , 1998, J. Electron. Test..
[3] Michael Gössel,et al. Self-Checking Comparator with One Periodic Output , 1996, IEEE Trans. Computers.
[4] Michael Nicolaidis. Fault secure property versus strongly code disjoint checkers , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[5] John Paul Shen,et al. Extraction and simulation of realistic CMOS faults using inductive fault analysis , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.
[6] Raminderpal Singh. Power Supply Noise in Future IC's: A Crystal Ball Reading , 2002 .
[7] H. B. Bakoglu,et al. Circuits, interconnections, and packaging for VLSI , 1990 .
[8] D. A. Anderson,et al. Design of self-checking digital networks using coding techniques , 1971 .
[9] Cecilia Metra,et al. On-line testing scheme for clock's faults , 1997, Proceedings International Test Conference 1997.
[10] Cecilia Metra,et al. On-line detection of logic errors due to crosstalk, delay, and transient faults , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).
[11] Kaushik Roy,et al. Estimation of switching noise on power supply lines in deep sub-micron CMOS circuits , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.
[12] S. Koeppe,et al. Optimal Layout to Avoid CMOS Stuck-Open Faults , 1987, 24th ACM/IEEE Design Automation Conference.
[13] Cecilia Metra,et al. Self-Checking Detection and Diagnosis of Transient, Delay, and Crosstalk Faults Affecting Bus Lines , 2000, IEEE Trans. Computers.
[14] Carlos Delgado Kloos,et al. Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.
[15] Dimitris Gizopoulos,et al. An asynchronous totally self-checking two-rail code error indicator , 1996, Proceedings of 14th VLSI Test Symposium.
[16] William C. Carter,et al. Design of dynamically checked computers , 1968, IFIP Congress.
[17] Cecilia Metra,et al. Highly testable and compact single output comparator , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).
[18] Cecilia Metra,et al. Sensing circuit for on-line detection of delay faults , 1996, IEEE Trans. Very Large Scale Integr. Syst..
[19] Cecilia Metra,et al. Compact and highly testable error indicator for self-checking circuits , 1996, Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
[20] Rosa Rodríguez-Montañés,et al. Bridging defects resistance measurements in a CMOS process , 1992, Proceedings International Test Conference 1992.
[21] Hannu Tenhunen,et al. Effective power and ground distribution scheme for deep submicron high speed VLSI circuits , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).
[22] Steffen Tarnick. Embedded Parity and Two-Rail TSC Checkers with Error-Memorizing Capability , 1998, VLSI Design.