Signal integrity issues in high-speed wireline links: analysis and integrated system solutions

This work focuses on the basic signal integrity issues of high-speed wireline links. It bridges the gap between optimum system design and circuit design for such links by: (1) understanding the effects of the system parameters on the bit error rate (BER), (2) introducing circuit architectures for the realization of systems that minimize the BER, and (3) demonstrating integrated circuit prototypes that verify the solutions. First, we develop a theory that analytically relates the data link BER to the system characteristics, e.g., the channel response, the pre-amplifier bandwidth, and the transmitter clock jitter. We generate the BER contours to find the optimum receiver bandwidth as well as the optimum sampling point and its associated timing margin. We also develop the theory of the data-dependent jitter (DDJ), which is a significant component of the timing jitter in high-speed links. We provide an analytical distribution function for the DDJ of an arbitrary linear time-invariant system and include the impact of the DDJ on the BER. Second, we propose a bandwidth enhancement method for wideband amplifiers. This is useful for the realization of high-speed links in technologies that suffer from large parasitic components. The method leverages two-port broadband matching to enable amplifier stages to achieve their maximum gain-bandwidth product. We demonstrate a 10Gb/s CMOS 0.18um amplifier with this technique that has 2.4 times the bandwidth improvement over a design that does not apply the technique. Third, we develop an eye-opening monitor (EOM) that enables full integration of adaptive equalizers. The EOM evaluates the signal eye diagram quality and reports a quantitative measure, which is correlated to the signal integrity. We demonstrate a prototype in 0.13um standard CMOS that operates up to 12.5Gb/s and has 68dB error dynamic range. Finally, we introduce an instantaneous clockless demultiplexer for burst-mode communication applications. We propose a clockless finite state machine that recovers and demultiplexes the received burst of data instantaneously. The architecture consists of a combinational logic structure and a bit-period-delayed feedback loop. We demonstrate a 1:2 clockless demultiplexer based on this concept in SiGe BiCMOS technology that operates at 7.5Gb/s.

[1]  Yi-Jen Chan,et al.  Bandwidth enhancement of transimpedance amplifier by a capacitive-peaking design , 1999, IEEE J. Solid State Circuits.

[2]  F. Gardner,et al.  Self-Noise in Synchronizers , 1980, IEEE Trans. Commun..

[3]  Burton R. Saltzberg,et al.  Timing recovery for synchronous binary data transmission , 1967 .

[4]  A. Hajimiri,et al.  Estimating data-dependent jitter of a general LTI system from step response , 2005, IEEE MTT-S International Microwave Symposium Digest, 2005..

[5]  E. Sackinger,et al.  Broadband Circuits for Optical Fiber Communication , 2005 .

[6]  Burton R. Saltzberg,et al.  Intersymbol interference error bounds with application to ideal bandlimited signaling , 1968, IEEE Trans. Inf. Theory.

[7]  S. Kobayashi,et al.  A multibitrate burst-mode CDR circuit with bit-rate discrimination function from 52 to 1244 Mb/s , 2001, IEEE Photonics Technology Letters.

[8]  Ali Hajimiri,et al.  Statistical analysis of integrated passive delay lines , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[9]  F. Buchali,et al.  Fast eye monitor for 10 Gbit/s and its application for optical PMD compensation , 2001, OFC 2001. Optical Fiber Communication Conference and Exhibit. Technical Digest Postconference Edition (IEEE Cat. 01CH37171).

[10]  Tim J. Nohara,et al.  A new signal quality degradation monitor for digital transmission channels , 1995, IEEE Trans. Commun..

[11]  Scott K. Reynolds,et al.  0.13∝m CMOS for Equalization of 10Gb/s Fiber-Optic Data Systems , 2005 .

[12]  R.D. Pollard,et al.  A filter synthesis technique applied to the design of multistage broadband microwave amplifiers , 2002, 2002 IEEE MTT-S International Microwave Symposium Digest (Cat. No.02CH37278).

[13]  H. Nyquist,et al.  Certain Topics in Telegraph Transmission Theory , 1928, Transactions of the American Institute of Electrical Engineers.

[14]  John F. Wakerly,et al.  Digital design - principles and practices , 1990, Prentice Hall Series in computer engineering.

[15]  T. P. Budka,et al.  Wide-bandwidth millimeter-wave bond-wire interconnects , 2001 .

[16]  Jan W. M. Bergmans,et al.  Adaptive characterization of write-precompensation circuits , 2003 .

[17]  Walter H. Ku,et al.  Optimum gain-bandwidth limitations of transistor amplifiers as reactively constrained active two-port networks , 1975 .

[18]  S. Gowda,et al.  Differential 4-tap and 7-tap transverse filters in SiGe for 10Gb/s multimode fiber optic link equalization , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[19]  R. Gibby,et al.  Some extensions of nyquist's telegraph transmission theory , 1965 .

[20]  Peter A. Franaszek,et al.  A DC-Balanced, Partitioned-Block, 8B/10B Transmission Code , 1983, IBM J. Res. Dev..

[21]  F. Buchali,et al.  Adaptive 1 and 2 stage PMD-compensators for 40 Gbit/s transmission using eye monitor feedback , 2003, OFC 2003 Optical Fiber Communications Conference, 2003..

[22]  D. J. Allstot,et al.  A 0.5-8.5 GHz fully differential CMOS distributed amplifier , 2002 .

[23]  Thomas Wong,et al.  Fundamentals of distributed amplification , 1993 .

[24]  Youngil Park,et al.  Optics layer protection of Gigabit-Ethernet system by monitoring optical signal quality , 2002 .

[25]  S. Pasupathy,et al.  Error rate monitoring for digital communications , 1982, Proceedings of the IEEE.

[26]  W. W. Hansen.  On Maximum Gain‐Band Width Product in Amplifiers , 1945 .

[27]  H. A. Wheeler.  Wide-band amplifiers for television , 1984 .

[28]  Vladimir Stojanovic,et al.  Modeling and analysis of high-speed links , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[29]  Thomas H. Lee,et al.  The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES , 2003 .

[30]  Ali Hajimiri,et al.  Multi–pole bandwidth enhancement technique for trans-impedance amplifiers , 2002 .

[31]  U. Langmann,et al.  A 10-Gb/s eye-opening monitor IC for decision-guided adaptation of the frequency response of an optical receiver , 2000, IEEE Journal of Solid-State Circuits.

[32]  B. Razavi.  Monolithic phase-locked loops and clock recovery circuits : theory and design , 1996 .

[33]  F. Buchali,et al.  A 40 Gb/s eye monitor and its application to adaptive PMD compensation , 2002, Optical Fiber Communication Conference and Exhibit.

[34]  H. W. Bode,et al.  Network analysis and feedback amplifier design , 1945 .

[35]  A. Rylyakov,et al.  A 10-Gb/s two-dimensional eye-opening monitor in 0.13-/spl mu/m standard CMOS , 2005, IEEE Journal of Solid-State Circuits.

[36]  A. Hajimiri,et al.  Bandwidth enhancement for transimpedance amplifiers , 2004, IEEE Journal of Solid-State Circuits.

[37]  F. K. Becker,et al.  Automatic equalization for digital communication , 1965 .

[38]  K. Feher,et al.  Techniques to Generate ISI and Jitter-Free Bandlimited Nyquist Signals and a Method to Analyze Jitter Effects , 1979, IEEE Trans. Commun..

[39]  Behzad Razavi.  A Versatile Clock Recovery Architecture and Monolithic Implementation , 1996 .

[40]  R. Bellman.  Perturbation techniques in mathematics, physics, and engineering , 1972 .

[41]  G. Cariolaro,et al.  A General Spectral Analysis of Time Jitter Produced in a Regenerative Repeater , 1977, IEEE Trans. Commun..

[42]  A.E. Willner,et al.  Optical performance monitoring , 2004, Journal of Lightwave Technology.

[43]  A. Rylyakov,et al.  A 10Gb/s eye-opening monitor in 0.13 /spl mu/m CMOS , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[44]  Norman C. Beaulieu,et al.  The evaluation of error probabilities for low-frequency attenuation channels , 1994, IEEE Trans. Commun..

[45]  A. Hajimiri,et al.  Jitter and phase noise in ring oscillators , 1999, IEEE J. Solid State Circuits.

[46]  K. Yamaguchi,et al.  Smart optical receiver with automatic decision threshold setting and retiming phase alignment , 1989 .

[47]  R. Fano.  Theoretical limitations on the broadband matching of arbitrary impedances , 1950 .

[48]  Carl W. Helstrom,et al.  Calculating Error Probabilities for Intersymbol and Cochannel Interference , 1986, IEEE Trans. Commun..

[49]  S. Chandrasekhar,et al.  A Si BiCMOS trans-impedance amplifier for 10 Gb SONET receiver , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[50]  Mihai Banu,et al.  A 660 Mb/s CMOS clock recovery circuit with instantaneous locking for NRZ data and burst-mode transmission , 1993, 1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[51]  Ali Hajimiri,et al.  Integrated transversal equalizers in high-speed fiber-optic systems , 2003, IEEE J. Solid State Circuits.

[52]  Yi Cai,et al.  Jitter testing for multi-Gigabit backplane SerDes - techniques to decompose and combine various types of jitter , 2002, Proceedings. International Test Conference.

[53]  A. A. Abidi.  Gigahertz transresistance amplifiers in fine line NMOS , 1984 .

[54]  Sang Joon Kim,et al.  A Mathematical Theory of Communication , 2006 .

[55]  U. Langmann,et al.  A 10 Gb/s eye opening monitor IC for decision-guided optimization of the frequency response of an optical receiver , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[56]  E. J. Griffin.  Theory and Design of Broadband Matching Networks , 1976 .

[57]  Stephen P. Boyd,et al.  Bandwidth extension in CMOS with optimized on-chip inductors , 2000, IEEE Journal of Solid-State Circuits.

[58]  K. Feher,et al.  On-Line Pseudo-Error Monitors for Digital Transmission Systems , 1978, IEEE Trans. Commun..

[59]  H. Rein,et al.  13 Gbit/s Si bipolar preamplifier for optical front ends , 1993 .

[60]  T. J. Gabara,et al.  150/30 Mb/s CMOS non-oversampled clock and data recovery circuits with instantaneous locking and jitter rejection , 1995, Proceedings ISSCC '95 - International Solid-State Circuits Conference.

[61]  Ali Hajimiri,et al.  Instantaneous clockless data recovery and demultiplexing , 2005, IEEE Transactions on Circuits and Systems II: Express Briefs.

[62]  G. Agrawal.  Fiber‐Optic Communication Systems , 2021 .

[63]  Ali Hajimiri,et al.  A 10Gb/s data-dependent jitter equalizer , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

[64]  F. Buchali,et al.  Eye monitoring in a 160 Gbit/s RZ field transmission system , 2001, Proceedings 27th European Conference on Optical Communication (Cat. No.01TH8551).

[65]  C. J. Byrne,et al.  Systematic jitter in a chain of digital regenerators , 1963 .

[66]  Y. Akazawa,et al.  A 156 Mbps CMOS clock recovery circuit for burst-mode transmission , 1996, 1996 Symposium on VLSI Circuits. Digest of Technical Papers.

[67]  Masashi Shimanouchi.  New paradigm for signal paths in ATE pin electronics are needed for serialcom device testing , 2002, Proceedings. International Test Conference.

[68]  E. D. Sunde,et al.  Self-timing regenerative repeaters , 1957 .

[69]  A. Hajimiri,et al.  Data-dependent jitter and crosstalk-induced bounded uncorrelated jitter in copper interconnects , 2004, 2004 IEEE MTT-S International Microwave Symposium Digest (IEEE Cat. No.04CH37535).

[70]  Gordon E. Moore.  Can Be Delayed , 2003 .

[71]  Toshio Kumamoto,et al.  A 10-b 50 MS/s 500-mW A/D converter using a differential-voltage subconverter , 1994 .

[72]  Alan V. Oppenheim,et al.  Discrete-Time Signal Pro-cessing , 1989 .

[73]  Behzad Razavi.  Design of intergrated circuits for optical communications , 2002 .

[74]  Dennis M. Petrich,et al.  A new method for jitter decomposition through its distribution tail fitting , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[75]  A. Hajimiri,et al.  Data-dependent jitter in serial communications , 2005, IEEE Transactions on Microwave Theory and Techniques.

[76]  G.E. Moore,et al.  No exponential is forever: but "Forever" can be delayed! [semiconductor industry] , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[77]  Hans-Martin Rein,et al.  Low-noise, high-gain Si-bipolar preamplifiers for 10 Gb/s optical-fiber links-design and realization , 1996 .

[78]  Ali Hajimiri,et al.  Capacity limits and matching properties of integrated capacitors , 2002, IEEE J. Solid State Circuits.

[79]  D. Youla,et al.  A New Theory of Broad-band Matching , 1964 .

[80]  Ali Hajimiri,et al.  Predicting data-dependent jitter , 2004, IEEE Transactions on Circuits and Systems II: Express Briefs.

[81]  W.R. Hewlett,et al.  Distributed Amplification , 1948, Proceedings of the IRE.

[82]  Norman C. Beaulieu,et al.  The evaluation of error probabilities for intersymbol and cochannel interference , 1991, IEEE Trans. Commun..

[83]  Jafar Savoj.  Clock and Data Recovery Circuits , 2008 .

[84]  Van Valkenburg,et al.  Analog Filter Design , 1982 .

[85]  Jan B. Wilstrup.  A method of serial data jitter analysis using one-shot time interval measurements , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[86]  Anatol I. Zverev,et al.  Handbook of Filter Synthesis , 1967 .

[87]  Yoshitaka Takasaki,et al.  Digital Transmission Design and Jitter Analysis , 1991 .

[88]  Jri Lee,et al.  A 10Gb/s CMOS adaptive equalizer for backplane applications , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[89]  S. Chandramouli,et al.  Realization of multigigabit channel equalization and crosstalk cancellation integrated circuits , 2004, IEEE Journal of Solid-State Circuits.

[90]  M. Zargari,et al.  A BiCMOS active substrate probe card technology for digital testing , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[91]  A. Hajimiri,et al.  An active analog delay and the delay reference loop , 2004, 2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers.

[92]  M. Banu,et al.  Clock recovery circuits with instantaneous locking , 1992 .

[93]  K. Maxham,et al.  Rockwell 135 Mbit/s lightwave system , 1984 .

[94]  S. Leigh,et al.  Probability and Random Processes for Electrical Engineering , 1989 .

[95]  Masashi Shimanouchi,et al.  An approach to consistent jitter modeling for various jitter aspects and measurement methods , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[96]  Fred Buchali,et al.  Dynamic adaptation of a PLC residual chromatic dispersion compensator at 40Gb/s , 2003, OFC 2003 Optical Fiber Communications Conference, 2003..

[97]  W. Bennett.  Statistics of regenerative digital transmission , 1958 .

[98]  V. Stojanovic,et al.  Equalization and clock recovery for a 2.5-10Gb/s 2-PAM/4-PAM backplane transceiver cell , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[99]  T. Lee,et al.  A 0.4-/spl mu/m CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter , 1999 .

[100]  アナルイ、ベーナム,et al.  Deterministic jitter equalizer , 2004 .

[101]  Kamran Azadet,et al.  Equalization and FEC techniques for optical transceivers , 2002, IEEE J. Solid State Circuits.

[102]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.