Hierarchical DFT with Combinational Scan Compression, Partition Chain and RPCT

Modular and hierarchical based test architecture are the two of the most common testing techniques used in complex SoC designs. However, modular test architectures uses an expensive (in terms of silicon area) test wrapper around each block. On the other hand hierarchical test architecture requires additional effort at block level to isolate each block from surrounding blocks and a TAM to perform scan compression. In this paper, we analyze the limitations of the modular test architecture. Based on the analysis, we propose a test plan for hierarchical test architecture by integrating partition chain, combinational scan compression and (RPCT) reduced pin count test. Experimental results show that approximately 50% of DFT area can be reduced using the partition chain as compared to standard test wrapper. It also demonstrates the feasibility of the proposed test plan using a commercial ATPG tool.

[1]  Tsvetomir Petrov,et al.  A Non-Intrusive Isolation Approach for Soft Cores , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[2]  Krishnendu Chakrabarty,et al.  Test planning for modular testing of hierarchical SOCs , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Benoit Nadeau-Dostie,et al.  Improved Core Isolation and Access for Hierarchical Embedded Test , 2009, IEEE Design & Test of Computers.

[4]  A. Gattiker,et al.  To DFT or not to DFT? , 1997, Proceedings International Test Conference 1997.

[5]  Qiang Xu,et al.  Time/area tradeoffs in testing hierarchical SOCs with hard mega-cores , 2004, 2004 International Conferce on Test.

[6]  Subhasish Mitra,et al.  X-compact: an efficient response compaction technique , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[7]  Darin Lee,et al.  Hierarchical DFT with enhancements for AC scan, test scheduling and on-chip compression - a case study , 2005, IEEE International Conference on Test, 2005..

[8]  Rohit Kapur,et al.  Scalable Adaptive Scan (SAS) , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[9]  Jeff Remmers,et al.  Hierarchical DFT methodology - a case study , 2004, 2004 International Conferce on Test.

[10]  Ming Zhang,et al.  Hierarchical Test Compression for SoC Designs , 2008, IEEE Design & Test of Computers.

[11]  T. Ziaja,et al.  Overview of DFT features of the Sun Microsystems Niagara2 CMP/CMT SPARC chip , 2008, 2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial.

[12]  Ran Ginosar,et al.  Cost considerations in network on chip , 2004, Integr..

[13]  Rohit Kapur,et al.  Evaluation of Entropy Driven Compression Bounds on Industrial Designs , 2008, 2008 17th Asian Test Symposium.

[14]  Yuejian Wu,et al.  Testing ASICs with multiple identical cores , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Nur A. Touba,et al.  Using Partial Isolation Rings to Test Core-Based Designs , 1997, IEEE Des. Test Comput..

[16]  Krishnendu Chakrabarty,et al.  Design and optimization of multi-level TAM architectures for hierarchical SOCs , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[17]  Nilanjan Mukherjee,et al.  Achieving High Test Quality with Reduced Pin Count Testing , 2005, 14th Asian Test Symposium (ATS'05).

[18]  Krishnendu Chakrabarty,et al.  Optimal test access architectures for system-on-a-chip , 2001, TODE.

[19]  Janak H. Patel,et al.  A case study on the implementation of the Illinois Scan Architecture , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[20]  Yervant Zorian,et al.  On using IEEE P1500 SECT for test plug-n-play , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[21]  V. Kamakoti,et al.  Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

[22]  Qiang Xu,et al.  Modular and rapid testing of SOCs with unwrapped logic blocks , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.