CMP Cache Architecture and the OpenMP Performance

Chip-multiprocessor (CMP) is regarded as the next generation of microprocessor architectures. For programming such machines OpenMP, a standard shared memory model, is a challenging candidate. A question arises: How to design the CMP hardware for high performance of OpenMP applications? This work explores the answer with cache architecture as a case study. Based on a simulator, we investigate how cache organization and reconfigurability influence the parallel execution of an OpenMP program. The achieved results can direct both architecture developers to determine hardware design and the programmers to generate efficient codes.

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