Optimal voltage testing for physically-based faults

In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus an two fault types: resistive bridges between gate outputs that cause pattern sensitive functional faults and opens in transmission gates that cause delay faults. In both cases, the traditional stuck at model is inadequate. The test vector to sensitize and propagate a resistive bridging fault is not unique. The traditional greedy test vector selection is optimistic, with some choices having poor real coverage. We realistically model the fault and fault coverage, and describe an optimal selection strategy. In a transmission gate with an open NMOS or PMOS device, the output voltage is degraded, increasing delay and reducing noise margin. We model this fault and show how low-voltage testing can be used to detect it. Our goal in applying these techniques to all important fault types is to maximize the real coverage of voltage tests, thereby minimizing the number of relatively slow Iddq tests required to achieve high quality.

[1]  Michel Renovell,et al.  CMOS bridging fault modeling , 1994, Proceedings of IEEE VLSI Test Symposium.

[2]  Jacob A. Abraham,et al.  Characterization and Testing of Physical Failures in MOS Logic Circuits , 1984, IEEE Design & Test of Computers.

[3]  Michel Renovell,et al.  The concept of resistance interval: a new parametric model for realistic resistive bridging fault , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[4]  Janak H. Patel,et al.  Fast and accurate CMOS bridging fault simulation , 1993, Proceedings of IEEE International Test Conference - (ITC).

[5]  Steven D. Millman,et al.  AN ACCURATE BRIDGING FAULT TEST PATTERN GENERATOR , 1991, 1991, Proceedings. International Test Conference.

[6]  Kenneth M. Wallquist,et al.  A general purpose I/sub DDQ/ measurement circuit , 1993, Proceedings of IEEE International Test Conference - (ITC).

[7]  Wojciech Maly,et al.  CMOS bridging fault detection , 1990, Proceedings. International Test Conference 1990.

[8]  Weiwei Mao,et al.  Detection of undetectable faults using IDDQ testing , 1992, Proceedings International Test Conference 1992.

[9]  Wojciech Maly,et al.  CMOS bridging fault detection , 1990, 1991, Proceedings. International Test Conference.

[10]  Kenneth M. Wallquist,et al.  A General Purpose IDDQ Measurement Circuit , 1993 .

[11]  Sudhakar M. Reddy,et al.  Testable Realizations for FET Stuck-Open Faults in CMOS Combinational Logic Circuits , 1986, IEEE Transactions on Computers.

[12]  Edward McCluskey,et al.  Designing CMOS Circuits for Switch-Level Testability , 1987, IEEE Design & Test of Computers.

[13]  Edward J. McCluskey,et al.  CMOS scan-path IC design for stuck-open fault testability , 1987 .

[14]  Edward J. McCluskey,et al.  Very-low-voltage testing for weak CMOS logic ICs , 1993, Proceedings of IEEE International Test Conference - (ITC).

[15]  Robert I. Damper,et al.  MOS Test Pattern Generation Using Path Algebras , 1987, IEEE Transactions on Computers.

[16]  Sudhakar M. Reddy,et al.  Fault Detection and Design For Testability of CMOS Logic Circuits , 1988 .

[17]  Wojciech Maly,et al.  Modeling of Lithography Related Yield Losses for CAD of VLSI Circuits , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[18]  Robert C. Aitken,et al.  Biased voting: A method for simulating CMOS bridging faults in the presence of variable gate logic thresholds , 1993, Proceedings of IEEE International Test Conference - (ITC).

[19]  Robert I. Damper,et al.  Physical faults in MOS circuits and their coverage by different fault models , 1988 .

[20]  R. Keith Treece,et al.  CMOS IC stuck-open-fault electrical effects and design considerations , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[21]  Anura P. Jayasumana,et al.  On Accuracy of Switch-Level Modeling of Bridging Faults in Complex Gates , 1987, 24th ACM/IEEE Design Automation Conference.

[22]  S.D. Millman,et al.  Diagnosing CMOS bridging faults with stuck-at fault dictionaries , 1990, Proceedings. International Test Conference 1990.

[23]  S. D. Millman,et al.  Accurate modeling and simulation of bridging faults , 1991, Proceedings of the IEEE 1991 Custom Integrated Circuits Conference.

[24]  G. G. Stokes.  "J." , 1890, The New Yale Book of Quotations.

[25]  Neil Weste,et al.  Principles of CMOS VLSI Design , 1985 .

[26]  Thomas M. Storey,et al.  STUCK FAULT AND CURRENT TESTING COMPARISON USING CMOS CHIP TEST , 1991, 1991, Proceedings. International Test Conference.

[27]  Michele Favalli,et al.  Parametric Bridging Fault Characterieation for the Fault Simulation of Library-Based ICs , 1992, Proceedings International Test Conference 1992.

[28]  Yves Crouzet,et al.  Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability , 1980, IEEE Transactions on Computers.

[29]  John M. Acken,et al.  Diagnosing CMOS bridging faults with stuck-at, IDDQ, and voting model fault dictionaries , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

[30]  Rosa Rodríguez-Montañés,et al.  Bridging defects resistance measurements in a CMOS process , 1992, Proceedings International Test Conference 1992.

[31]  Hussein T. Mouftah,et al.  Modelling and test generation for MOS transmission gate stuck-open faults , 1992 .

[32]  John M. Acken,et al.  Fault Model Evolution For Diagnosis: Accuracy vs Precision , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[33]  Vishwani D. Agrawal,et al.  Modeling and Test Generation Algorithms for MOS Circuits , 1985, IEEE Transactions on Computers.

[34]  Sudhakar M. Reddy,et al.  On Testable Design for CMOS Logic Circuits , 1983, International Test Conference.