Performance of a shared memory system for vector multiprocessors

The subject of multistage interconnection networks (MINs) has been extensively studied in the lazt ten years and has gained even more attention recently with increased interest in large-scale shared memory multiprocessors. Several multiprocessors are under construction using packet-switched multistage networks [4,5,11]. While some theoretical results have been obtained about the behavior of MINs [1,3,6,8,9,10], and their limitations along with possible corrections for practical systems have been discussed [12], many questions still remain unanswered. In particular, the performance of MIN’s supporting vector multiprocessors is an issue of growing importance as the number of such machines increases. In this paper we will present results showing the behavior of not only a MIN but of an entire shared memory system obtained through simulation. Our goal is to evaluate the performance and interaction between components of such a system, based on realistic hardware assumptions and driven by user programs. To achieve this we have developed a parallel register-transfer level simulator of interconnection networks and an interleaved shared memory. The simulator itself runs on a multiprocessor (Alliant FX/8). We study non-uniform, burst traffic as exhibjted by prefetch or vector units in each processor. Because the exact behavior of the hardware is simulated, we also obtain a time dependent descrip tion of system performance. In the first part of this paper we describe the sys-