Time-constrained systems validation using mda model transformation. A railway case study

The aim of the work presented in this paper is to introduce a method for verifying temporal requirements of time-constrained systems. The method allows the automated veri cation of temporal require- ments, initially expressed in a semi-formal formalism, through model transformation and model-checking. For the several advantages it o ers, UML has been used for the rst-step speci cation translated thereafter into a formal speci cation. Concretely, the input model for the transformation is an UML State Machines (SM) depicting the system temporal requirements. SM has a rich semantics and o ers big exibility. On the other hand, Timed Automata has proven to be useful for verifying temporal constraints and several veri cation tools are based on this formal notation. The rst contribution of this paper consists of developing an algorithm for transforming UML SM with time annotations into Timed Automata. Once the temporal requirements of the studied system are speci ed, the veri cation is proceeded on the basis of some observation patterns we have developed. The global approach is illustrated through the level crossing case study.

[1]  Kurt Geihs,et al.  Model Metamorphosis , 2003, IEEE Softw..

[2]  Mohamed Ghazel,et al.  Validating time-constrained systems using UML statecharts patterns and timed automata observers , 2009 .

[3]  Ursula Goltz,et al.  Timed Sequence Diagrams and Tool-Based Analysis - A Case Study , 1999, UML.

[4]  Rajeev Alur,et al.  A Theory of Timed Automata , 1994, Theor. Comput. Sci..

[5]  Cyrille Artho,et al.  Architecture-aware Partial Order Reduction to Accelerate Model Checking of Networked Programs , 2008, 2008 Ninth ACIS International Conference on Software Engineering, Artificial Intelligence, Networking, and Parallel/Distributed Computing.

[6]  Stephan Merz,et al.  Model Checking - Timed UML State Machines and Collaborations , 2002, FTRTFT.

[7]  Mieke Massink,et al.  Automatic Verication of a Behavioural Subset of UML Statechart Diagrams Using the SPIN , 1999 .

[8]  Amir Pnueli,et al.  On the Formal Semantics of Statecharts (Extended Abstract) , 1987, LICS.

[9]  Stephan Merz,et al.  Model checking UML state machines and collaborations , 2001, Workshop on Software Model Checking @ CAV.

[10]  Angelo Gargantini,et al.  Using Spin to Generate Testsfrom ASM Specifications , 2003, Abstract State Machines.

[11]  Johan Lilius,et al.  Formalising UML State Machines for Model Checking , 1999, UML.

[12]  Yves Le Traon,et al.  Evaluating Context Descriptions and Property Definition Patterns for Software Formal Validation , 2009, MoDELS.

[13]  S. Ramesh,et al.  Model Checking of Statechart Models: Survey and Research Directions , 2004, ArXiv.

[14]  Iulian Ober,et al.  Validation of UML Models via a Mapping to Communicating Extended Timed Automata , 2004, SPIN.

[15]  Diego Latella,et al.  Automatic Verification of a Behavioural Subset of UML Statechart Diagrams Using the SPIN Model-checker , 1999, Formal Aspects of Computing.

[16]  Stephen J. Mellor,et al.  MDA Distilled Principles Of Model-Driven Architecture , 2004 .