Dual stress capping layer enhancement study for hybrid orientation finFET CMOS technology

3D stress in FinFET and tri-gate FET structures induced by a tensile or compressive capping layer is studied via simulation. The classic bulk-Si piezoresistance model is then used to predict the impact on carrier mobilities. A tensile capping layer is expected to provide dramatic enhancements (>100%) in electron mobility for a (100)-sidewall fin with lang100rang current flow, while a compressive capping layer is expected to provide modest enhancement (<25%) in hole mobility for a (110)-sidewall fin with lang110rang current flow. Mobility enhancement will be greater for fins with higher aspect ratio, so that a stressed capping layer is expected to be more effective for enhancing FinFET performance

[1]  Jeffrey Bokor,et al.  Extremely scaled silicon nano-CMOS devices , 2003, Proc. IEEE.

[2]  J. Kavalieros,et al.  High performance fully-depleted tri-gate CMOS transistors , 2003, IEEE Electron Device Letters.

[3]  Y. Kanda,et al.  A graphical representation of the piezoresistance coefficients in silicon , 1982, IEEE Transactions on Electron Devices.

[4]  M. Bohr,et al.  A logic nanotechnology featuring strained-silicon , 2004, IEEE Electron Device Letters.

[5]  V. Trivedi,et al.  Pragmatic design of nanoscale multi-gate CMOS , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[6]  Charles S. Smith Piezoresistance Effect in Germanium and Silicon , 1954 .

[7]  Chenming Hu,et al.  Sub-60-nm quasi-planar FinFETs fabricated using a simplified process , 2001, IEEE Electron Device Letters.

[8]  Hisashi Hara,et al.  Mobility Anisotropy of Electrons in Inversion Layers on Oxidized Silicon Surfaces , 1971 .