55nm CMOS 12-bit 250MHz digital-to-analog converter with dynamic voltage scaling (DVS) technique through single-inductor dual-output (SIDO) converter

This 55nm CMOS 12-bit current-steering DAC directly powered by the single-inductor dual-output (SIDO) switching DC-DC converter with the dynamic voltage scaling (DVS) technique improves the DAC's power efficiency by 25% and achieves 65.34dB SFDR. The proposed 3S method, including separating, splitting, and shifting, effectively reduces the current mismatching within 0.2% and suppresses the switching noise interference from the SIDO converter. The 12-bit DAC and SIDO module achieve compatible performance compare to the tradition method and has the benefit of area and energy efficiency.

[1]  Jae-Woo Lee,et al.  Multiple-output step-up/down switching DC-DC converter with vestigial current control , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[2]  Ke-Horng Chen,et al.  A DVS embedded power management for high efficiency integrated SOC in UWB system , 2009 .

[3]  John D. Hyde,et al.  A 300-MS/s 14-bit digital-to-analog converter in logic CMOS , 2003, IEEE J. Solid State Circuits.

[4]  Klaas Bult,et al.  A 10b , 500-MSample / s CMOS DAC in 0 . 6 mm , 1999 .

[5]  Ke-Horng Chen,et al.  Minimized transient and steady-state cross regulation in 55nm CMOS single-inductor dual-output (SIDO) step-down DC-DC converter , 2010, 2010 IEEE Asian Solid-State Circuits Conference.

[6]  K. Bult,et al.  A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2 , 1998, IEEE J. Solid State Circuits.

[7]  Chi-Ying Tsui,et al.  A pseudo-CCM/DCM SIMO switching converter with freewheel switching , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[8]  Gyu-Hyeong Cho,et al.  A Single-Inductor Switching DC–DC Converter With Five Outputs and Ordered Power-Distributive Control , 2007, IEEE Journal of Solid-State Circuits.