Requirements for ultra-thin-film devices and new materials for the CMOS roadmap

Abstract For the first time various devices architectures (bulk, SOI and SON) and process modules (metal gate, strained-Si channel) are compared in a consistent way using the same analytical tool. This analysis shows on one hand that the conventional bulk cannot match the requirements throughout the entire ITRS’01 roadmap, but on the other hand it gives clear guidelines on device architectures permitting to do so. In other words, this paper puts forward a device architecture roadmap and shows precisely which architectures, modules and materials will be needed at a given CMOS node. This message analysis may be of importance for semiconductor manufacturers, equipment makers and SOI wafer providers.

[1]  M. Jurczak,et al.  Silicon-on-Nothing (SON)-an innovative process for advanced CMOS , 2000 .

[2]  M. Haond,et al.  SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi/sub 2/) polysilicon on 5 nm-thick Si-films: the simplest way to integration of metal gates on thin FD channels , 2002, Digest. International Electron Devices Meeting,.

[3]  G. Knoblinger,et al.  Integration of high-performance, low-leakage and mixed signal features into a 100 nm CMOS technology , 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

[4]  H. Nambu,et al.  UX6-100 nm generation CMOS integration technology with Cu/low-k interconnect , 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

[5]  T. Skotnicki Heading for decananometer CMOS - Is navigation among icebergs still a viable strategy? , 2000, 30th European Solid-State Device Research Conference.

[6]  P. Abramowitz,et al.  A 100 nm copper/low-k bulk CMOS technology with multi Vt and multi gate oxide integrated transistors for low standby power, high performance and RF/analog system on chip applications , 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

[7]  Wei Jin,et al.  High performance 50 nm CMOS devices for microprocessor and embedded processor core applications , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[8]  Y. Sambonsugi,et al.  A 100 nm CMOS technology with "sidewall-notched" 40 nm transistors and SiC-capped Cu/VLK interconnects for high performance microprocessor applications , 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

[9]  L. T. Su,et al.  Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's , 1994, IEEE Electron Device Letters.

[10]  D. Reber,et al.  A high density 0.10 /spl mu/m CMOS technology using low K dielectric and copper interconnect , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[11]  K. Kim,et al.  60 nm gate length dual-Vt CMOS for high performance applications , 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

[12]  M. Ieong,et al.  Examination of hole mobility in ultra-thin body SOI MOSFETs , 2002, Digest. International Electron Devices Meeting,.

[13]  Chenming Hu,et al.  The impact of device scaling and power supply change on CMOS gate performance , 1996, IEEE Electron Device Letters.

[14]  T. Skotnicki,et al.  A new analog/digital CAD model for sub-halfmicron MOSFETs , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.

[15]  Thomas Skotnicki Analysis of the silicon technology roadmap How far can CMOS go , 2000 .

[16]  D. Frank,et al.  Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET's at the 25 nm channel length generation , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).

[17]  R. Koh Buried Layer Engineering to Reduce the Drain-Induced Barrier Lowering of Sub-0.05 µm SOI-MOSFET , 1999 .

[18]  M. Hussein,et al.  An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7 - 1.4 V , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[19]  T. Numata,et al.  Experimental study on carrier transport mechanism in ultrathin-body SOI nand p-MOSFETs with SOI thickness less than 5 nm , 2002, Digest. International Electron Devices Meeting,.

[20]  A. Mocuta,et al.  Mobility enhancement in strained Si NMOSFETs with HfO/sub 2/ gate dielectrics , 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

[21]  T. Skotnicki Polysilicon gate with depletion-or-metallic gate with buried channel: what evil worse ? , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[22]  Sorin Cristoloveanu,et al.  Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture , 2002 .