TOWARDS A FRAMEWORK FOR THE DISTRIBUTED SIMULATION OF ASYNCHRONOUS HARDWARE

Synchronous VLSI design is approaching a critical point, with clock distribution becoming an increasingly costly and complicated issue and power consumption rapidly emerging as a major concern. The last decade has witnessed a resurgence of interest in asynchronous logic which promises to liberate digital design from the inherent problems of synchronous systems. This activity has revealed a need for modelli ng and simulation techniques suitable for the asynchronous design style. The concurrent process algebra Communicating Sequential Processes (CSP) is particularly suitable for the specification of asynchronous systems. This paper discusses a framework for the distributed simulation of asynchronous hardware, adopting Balsa, a CSP-like notation, as a hardware description language.

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