Every single manufactured chip must be tested for manufacturing defects, and today, it is reported that 30% of the overall production cost is due to testing. Testing cost of a chip is directly related to the time it takes because expensive automatic test equipment (ATE) is used to test these circuits. Design for Test (DFT) techniques consist of the design of on-chip hardware blocks along with accompanying the software CAD tools that enable the high-quality and cost-effective test of manufactured chips for manufacturing defects. This paper aims at reducing the time needed for test without increasing the power wasted during the test. The power consumption of a circuit under test (CUT) during the test can go beyond the power consumption in the functional mode of operation due to high switching activity needed to accomplish high test coverage for the CUT. In this paper, a novel transistor level implementation of scan flip-flop (SFF) design is proposed to reduce the test time of each SFF as a result reduction in overall test time of the scan chain.
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