VTR 8: High Performance CAD and Customizable FPGA Architecture Modelling

KEVIN E. MURRAY, University of Toronto, Canada OLEG PETELIN, University of Toronto, Canada SHENG ZHONG, University of Toronto, Canada JIA MIN WANG, University of Toronto, Canada MOHAMED ELDAFRAWY, University of Toronto, Canada JEAN-PHILIPPE LEGAULT, University of New Brunswick, Canada EUGENE SHA, University of Toronto, Canada AARON G. GRAHAM, University of New Brunswick, Canada JEAN WU, University of Toronto, Canada MATTHEW J. P. WALKER, University of Toronto, Canada HANQING ZENG, University of Toronto, Canada PANAGIOTIS PATROS, University of New Brunswick, Canada JASON LUU, Intel Programmable Solutions Group, Canada KENNETH B. KENT, University of New Brunswick, Canada VAUGHN BETZ, University of Toronto, Canada

[1]  Nils J. Nilsson,et al.  A Formal Basis for the Heuristic Determination of Minimum Cost Paths , 1968, IEEE Trans. Syst. Sci. Cybern..

[2]  Ralph Johnson,et al.  design patterns elements of reusable object oriented software , 2019 .

[3]  Carl Ebeling,et al.  PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs , 1995, Third International ACM Symposium on Field-Programmable Gate Arrays.

[4]  Chak-Kuen Wong,et al.  Universal switch modules for FPGA design , 1996, TODE.

[5]  Vaughn Betz,et al.  VPR: A new packing, placement and routing tool for FPGA research , 1997, FPL.

[6]  Steven J. E. Wilton,et al.  Architectures and algorithms for field-programmable gate arrays with embedded memory , 1997 .

[7]  Vaughn Betz,et al.  A fast routability-driven router for FPGAs , 1998, FPGA '98.

[8]  André DeHon,et al.  Balancing interconnect and computation in a reconfigurable computing array (or, why you don't really want 100% LUT utilization) , 1999, FPGA '99.

[9]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[10]  Vaughn Betz,et al.  Automatic generation of FPGA routing architectures from high-level descriptions , 2000, FPGA '00.

[11]  Malgorzata Marek-Sadowska,et al.  Efficient circuit clustering for area and power reduction in FPGAs , 2002, FPGA '02.

[12]  Vaughn Betz,et al.  The stratixπ routing and logic architecture , 2003, FPGA '03.

[13]  Jason Cong,et al.  Simultaneous Timing Driven Clustering and Placement for FPGAs , 2004, FPL.

[14]  Kia Bazargan,et al.  HARP: hard-wired routing pattern FPGAs , 2005, FPGA '05.

[15]  Nick Knupffer.  Intel Corporation , 2018, The Grants Register 2019.

[16]  Carl Ebeling,et al.  Architecture-adaptive routability-driven placement for FPGAs , 2005, International Conference on Field Programmable Logic and Applications, 2005..

[17]  Mike Hutton,et al.  Efficient static timing analysis and applications using edge masks , 2005, FPGA '05.

[18]  Jason Cong,et al.  FPGA Design Automation: A Survey , 2006, Found. Trends Electron. Des. Autom..

[19]  Andrew A. Kennings,et al.  Improving Timing-Driven FPGA Packing with Physical Information , 2007, 2007 International Conference on Field Programmable Logic and Applications.

[20]  Robert K. Brayton,et al.  ABC: An Academic Industrial-Strength Verification Tool , 2010, CAV.

[21]  Kenneth B. Kent,et al.  Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research , 2010, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines.

[22]  Vaughn Betz,et al.  A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs , 2010, FPGA '10.

[23]  Herman Lam,et al.  Comparative analysis of HPC and accelerator devices: Computation, memory, I/O, and power , 2010, 2010 FOURTH INTERNATIONAL WORKSHOP ON HIGH-PERFORMANCE RECONFIGURABLE COMPUTING TECHNOLOGY AND APPLICATIONS (HPRCTA).

[24]  Peter M. Athanas,et al.  Torc: towards an open-source tool flow , 2011, FPGA '11.

[25]  Kenneth B. Kent,et al.  VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling , 2011, TRETS.

[26]  Guy Lemieux,et al.  Deterministic Timing-Driven Parallel Placement by Simulated Annealing Using Half-Box Window Decomposition , 2011, 2011 International Conference on Reconfigurable Computing and FPGAs.

[27]  Brent E. Nelson,et al.  RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs , 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

[28]  Raphael Rubin,et al.  Timing-driven pathfinder pathology and remediation: quantifying and reducing delay noise in VPR-pathfinder , 2011, FPGA '11.

[29]  Vaughn Betz,et al.  Design tradeoffs for hard and soft FPGA-based Networks-on-Chip , 2012, 2012 International Conference on Field-Programmable Technology.

[30]  Steven J. E. Wilton,et al.  VersaPower: Power estimation for diverse FPGA architectures , 2012, 2012 International Conference on Field-Programmable Technology.

[31]  Kenneth B. Kent,et al.  The VTR project: architecture and CAD for FPGAs from verilog to routing , 2012, FPGA '12.

[32]  Paolo Ienne,et al.  Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones , 2012, FPGA '12.

[33]  Vaughn Betz,et al.  Titan: Enabling large and complex benchmarks in academic CAD , 2013, 2013 23rd International Conference on Field programmable Logic and Applications.

[34]  Vaughn Betz,et al.  COFFE: Fully-automated transistor sizing for FPGAs , 2013, 2013 International Conference on Field-Programmable Technology (FPT).

[35]  Steven J. E. Wilton,et al.  Escaping the Academic Sandbox: Realizing VPR Circuits on Xilinx Devices , 2013, 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines.

[36]  David M. Lewis,et al.  Architectural enhancements in Stratix V™ , 2013, FPGA '13.

[37]  Jason Luu,et al.  Architecture-Aware Packing and CAD Infrastructure for Field-Programmable Gate Arrays , 2014 .

[38]  Yao-Wen Chang,et al.  Efficient and effective packing and analytical placement for large-scale heterogeneous FPGAs , 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[39]  Steven J. E. Wilton,et al.  Incremental Trace-Buffer Insertion for FPGA Debug , 2014, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[40]  Hao Jun Liu,et al.  Archipelago - An Open Source FPGA with Toolflow Support , 2014 .

[41]  Sarma Vrudhula,et al.  A fast, energy efficient, field programmable threshold-logic array , 2014, 2014 International Conference on Field-Programmable Technology (FPT).

[42]  Giovanni De Micheli,et al.  A high-performance low-power near-Vt RRAM-based FPGA , 2014, 2014 International Conference on Field-Programmable Technology (FPT).

[43]  Jason Luu,et al.  Towards interconnect-adaptive packing for FPGAs , 2014, FPGA.

[44]  Bo Yan,et al.  On Hard Adders and Carry Chains in FPGAs , 2014, 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines.

[45]  Paolo Ienne,et al.  Revisiting and-inverter cones , 2014, FPGA.

[46]  Gary William Grewal,et al.  A scalable, serially-equivalent, high-quality parallel placement methodology suitable for modern multicore and GPU architectures , 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

[47]  Sen Wang,et al.  VTR 7.0: Next Generation Architecture and CAD System for FPGAs , 2014, TRETS.

[48]  Wenyi Feng,et al.  Rent's rule based FPGA packing for routability optimization , 2014, FPGA.

[49]  Vaughn Betz,et al.  Speeding Up FPGA Placement: Parallel Algorithms and Methods , 2014, 2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines.

[50]  John Teifel,et al.  Improving ASIC Reuse with Embedded FPGA Fabrics , 2015 .

[51]  Yajun Ha,et al.  ParaLaR: A parallel FPGA router based on Lagrangian relaxation , 2015, 2015 25th International Conference on Field Programmable Logic and Applications (FPL).

[52]  Vaughn Betz,et al.  Robust Optimization of Multiple Timing Constraints , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[53]  Eddie Hung.  Mind the (synthesis) gap: Examining where academic FPGA tools lag behind industry , 2015, 2015 25th International Conference on Field Programmable Logic and Applications (FPL).

[54]  Vaughn Betz,et al.  Timing-Driven Titan: Enabling Large Benchmarks and Exploring the Gap between Academic and Commercial CAD , 2015, TRETS.

[55]  Brent E. Nelson,et al.  RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs , 2015, FPGA.

[56]  Deming Chen,et al.  A scalable and high-density FPGA architecture with multi-level phase change memory , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[57]  André DeHon,et al.  Impact of Memory Architecture on FPGA Energy Consumption , 2015, FPGA.

[58]  Yao-Wen Chang,et al.  Routing-architecture-aware analytical placement for heterogeneous FPGAs , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[59]  Yu Wang,et al.  EURECA: On-Chip Configuration Generation for Effective Dynamic Data Access , 2015, FPGA.

[60]  Hossein Asadi,et al.  An efficient reconfigurable architecture by characterizing most frequent logic functions , 2015, 2015 25th International Conference on Field Programmable Logic and Applications (FPL).

[61]  Eric S. Chung,et al.  A reconfigurable fabric for accelerating large-scale datacenter services , 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).

[62]  Farheen Fatima Khan,et al.  An evaluation on the accuracy of the minimum width transistor area models in ranking the layout area of FPGA architectures , 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

[63]  Oleg Petelin.  CAD tools and architectures for improved FPGA interconnect , 2016 .

[64]  Vaughn Betz,et al.  Multiple Dice Working as One: CAD Flows and Routing Architectures for Silicon Interposer FPGAs , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[65]  Russell Tessier,et al.  Effects of I/O routing through column interfaces in embedded FPGA fabrics , 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

[66]  Carl Ebeling,et al.  Stratix™ 10 High Performance Routable Clock Networks , 2016, FPGA.

[67]  Vaughn Betz,et al.  The speed of diversity: Exploring complex FPGA routing topologies for the global metal layer , 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

[68]  Christina Delimitrou,et al.  DRAF: A Low-Power DRAM-Based Reconfigurable Acceleration Fabric , 2016, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA).

[69]  Dimitrios Soudris,et al.  A Customizable Framework for Application Implementation onto 3-D FPGAs , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[70]  Jason Luu,et al.  Hybrid LUT/Multiplexer FPGA Logic Architectures , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[71]  Yong Lian,et al.  High-Density and High-Reliability Nonvolatile Field-Programmable Gate Array With Stacked 1D2R RRAM Array , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[72]  Jörg Henkel,et al.  Stress-aware routing to mitigate aging effects in SRAM-based FPGAs , 2016, 2016 26th International Conference on Field Programmable Logic and Applications (FPL).

[73]  Valavan Manohararajah,et al.  The Stratix™ 10 Highly Pipelined FPGA Architecture , 2016, FPGA.

[74]  Paolo Ienne,et al.  Evaluating FPGA clusters under wide ranges of design parameters , 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

[75]  Jason H. Anderson,et al.  Leveraging Unused Resources for Energy Optimization of FPGA Interconnect , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[76]  Mirjana Stojilović,et al.  Parallel FPGA routing: Survey and challenges , 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

[77]  Jason Helge Anderson,et al.  Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow , 2017, ACM Trans. Reconfigurable Technol. Syst..

[78]  Hossein Asadi,et al.  PEAF: A Power-Efficient Architecture for SRAM-Based FPGAs Using Reconfigurable Hard Logic Design in Dark Silicon Era , 2017, IEEE Transactions on Computers.

[79]  Guojie Luo,et al.  Corolla: GPU-Accelerated FPGA Routing Based on Subgraph Dynamic Expansion , 2017, FPGA.

[80]  Vaughn Betz,et al.  Don't Forget the Memory: Automatic Block RAM Modelling, Optimization, and Architecture Exploration , 2017, FPGA.

[81]  Hiroyuki Ochi,et al.  Placement algorithm for mixed-grained reconfigurable architecture with dedicated carry chain , 2017, 2017 30th IEEE International System-on-Chip Conference (SOCC).

[82]  Peter R. Kinget,et al.  FPGA with Improved Routability and Robustness in 130nm CMOS with Open-Source CAD Targetability , 2017, ArXiv.

[83]  Zhiru Zhang,et al.  A Parallel Bandit-Based Approach for Autotuning FPGA Compilation , 2017, FPGA.

[84]  Yiorgos Makris,et al.  A field programmable transistor array featuring single-cycle partial/full dynamic reconfiguration , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[85]  Jianping Hu,et al.  RBSA: Range-based simulated annealing for FPGA placement , 2017, 2017 International Conference on Field Programmable Technology (ICFPT).

[86]  Hossein Asadi,et al.  A power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon era , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[87]  Wei Li,et al.  NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element , 2017, FPGA.

[88]  Elias Vansteenkiste,et al.  Liquid: High quality scalable placement for large heterogeneous FPGAs , 2017, 2017 International Conference on Field Programmable Technology (ICFPT).

[89]  Akash Kumar,et al.  ParaDRo: A Parallel Deterministic Router Based on Spatial Partitioning and Scheduling , 2018, FPGA.

[90]  Vaughn Betz,et al.  Tatum: Parallel Timing Analysis for Faster Design Cycles and Improved Optimization , 2018, 2018 International Conference on Field-Programmable Technology (FPT).

[91]  Hari Angepat,et al.  Serving DNNs in Real Time at Datacenter Scale with Project Brainwave , 2018, IEEE Micro.

[92]  Kenneth B. Kent,et al.  Towards Trainable Synthesis for Optimized Circuit Deployment on FPGA , 2018, 2018 International Symposium on Rapid System Prototyping (RSP).

[93]  Elias Vansteenkiste,et al.  How Preserving Circuit Design Hierarchy During FPGA Packing Leads to Better Performance , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[94]  Eddie Hung,et al.  Yosys+nextpnr: An Open Source Framework from Verilog to Bitstream for Commercial FPGAs , 2019, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

[95]  Ken Mai,et al.  An Inherently Secure FPGA using PUF Hardware-Entanglement and Side-Channel Resistant Logic in 65nm Bulk CMOS , 2019, ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC).

[96]  Chirag Ravishankar,et al.  Xilinx Adaptive Compute Acceleration Platform: VersalTM Architecture , 2019, FPGA.

[97]  Linda L. Shen,et al.  Becoming More Tolerant: Designing FPGAs for Variable Supply Voltage , 2019, 2019 29th International Conference on Field Programmable Logic and Applications (FPL).

[98]  Vaughn Betz,et al.  Adaptive FPGA Placement Optimization via Reinforcement Learning , 2019, 2019 ACM/IEEE 1st Workshop on Machine Learning for CAD (MLCAD).

[99]  Sagheer Ahmad,et al.  Network-on-Chip Programmable Platform in VersalTM ACAP Architecture , 2019, FPGA.

[100]  Elias Vansteenkiste,et al.  CRoute: A Fast High-Quality Timing-Driven Connection-Based FPGA Router , 2019, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

[101]  Zhiru Zhang,et al.  Painting on Placement: Forecasting Routing Congestion using Conditional Generative Adversarial Nets , 2019 .

[102]  Kenneth B. Kent,et al.  Improving Digital Circuit Simulation with Batch-Parallel Logic Evaluation , 2019, 2019 22nd Euromicro Conference on Digital System Design (DSD).

[103]  D. Wentzlaff,et al.  PRGA: An Open-source Framework for Building and Using Custom FPGAs , 2019 .

[104]  P. Gaillardon,et al.  OpenFPGA: a Complete Open Source Framework for FPGA Prototyping , 2019 .

[105]  Vaughn Betz,et al.  COFFE 2: Automatic Modelling and Optimization of Complex and Heterogeneous FPGA Architectures , 2019, TRETS.

[106]  Lingli Wang,et al.  Bent Routing Pattern for FPGA , 2019, 2019 29th International Conference on Field Programmable Logic and Applications (FPL).

[107]  Kenneth B. Kent,et al.  Optimizing FPGA Logic Block Architectures for Arithmetic , 2020, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[108]  Sheng Zhong,et al.  AIR: A Fast but Lazy Timing-Driven FPGA Router , 2020, 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC).