Characterization of drop impact survivability of a 3D CSP stack module

Chip scale packages (CSPs) are widely used in miniaturized electronic systems, and the performance advantages and reliability of single layer packages have been well studied for consumer applications. Three dimensional stacked modules allow for further miniaturization while retaining manufacturability and performance advantages, but they are not yet as widely used or investigated as single layer packages. Of particular concern is the survivability of a board mounted, stacked module under board level drop impact and shock loading, which may soon be of great importance in consumer, industrial and military applications. A CSP stack module is fabricated by stacking several CSPs to achieve high-density 3D systems without increasing the package's footprint. But it also introduces more probabilities of mechanical failure including drop impact-induced malfunction in solder interconnections. In order to evaluate the survivability of a stacked package, we have developed a model for a two level CSP stack module attached to a FR-4 board following the JEDEC standard. With this assembly undergoing drop impact in the 0deg orientation (horizontal drop) under two types of impulse loads, we discuss the results of board-level impacts theoretically and numerically. Our results suggest that (1) the solder balls at the first CSP level are the determining factor in package reliability, (2) the first CSP level is most susceptible to damage and failure for the horizontal drop, and (3) damages in the higher level solder joints are due to a combination of vibration induced and stress wave induced stresses.