On-chip decoupling zone for package-stress reduction

The authors report the reduction of package stresses by introducing a decoupling zone directly around a sensor structure. Different geometries of the decoupling zones are compared, using the finite element method (FEM) and analytical models. Reduction factors over 1000 and higher can be realized by using an axisymmetrical V-corrugation. A design rule to optimize the reduction for the V-corrugation is given. This rule is based on analytical calculations and verified by FEM-simulations. Finally, it is shown that the thickness of a backplate, mounted to the sensor chip, can be optimized for minimal thermal stresses in the sensor.<<ETX>>